1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey...

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1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis

Transcript of 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey...

Page 1: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis 2.0

Byron Cook and Satnam Singhwith Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis

Page 2: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Explosion of advances in program verification

Impossible 10 years ago, standard today SLAM, SpaceInvader, ARMC, Thor, RGSep, TERMINATOR, etc WP synthesis, WLP synthesis,

Challenges in automatic program verification Concurrency Data structures Scalability/precision Productization New applications

Page 3: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Beyond proving correctness

Can we use these techniques elsewhere? Compilers ? Operating systems? Language runtimes?

Current focus: hardware synthesis Synthesis for heap-based programs using techniques from

termination provers Automatically parallelize circuits, and localize memories on

chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using

complexity analysis

Page 4: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?

Current focus: hardware synthesis Synthesis for heap-based programs using techniques from

termination provers Automatically parallelize circuits, and localize memories on

chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using

complexity analysis

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Beyond proving correctness

Page 5: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?

Current focus: hardware synthesis Synthesis for heap-based programs using techniques from

termination provers Automatically parallelize circuits, and localize memories on

chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using

complexity analysis

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Beyond proving correctness

Page 6: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?

Current focus: hardware synthesis Synthesis for heap-based programs using techniques from

termination provers Automatically parallelize circuits, and localize memories on

chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using

complexity analysis

6

Beyond proving correctness

Page 7: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Can we use these techniques elsewhere? Compilers ? Operating systems? Language runtimes?

Current focus: hardware synthesis Synthesis for heap-based programs using techniques from

termination provers Automatically parallelize circuits, and localize memories on

chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using

complexity analysis

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Beyond proving correctness

Page 8: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

HardwareSynthesis

Page 9: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

HardwareSynthesis

Page 10: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

HardwareSynthesis

Page 11: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

HardwareSynthesis

Page 12: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

HardwareSynthesis

Page 13: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

HardwareSynthesis

Page 14: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

HardwareSynthesis

Page 15: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

HardwareSynthesis

Page 16: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

Page 17: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass

error

XX

Page 18: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass

error

XX

Page 19: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesisXX

Page 20: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

Page 21: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

pass

Page 22: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

pass

Page 23: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

pass

Page 24: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

pass

Page 25: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

pass

Page 26: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

pass

Page 27: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

pass

Page 28: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

HardwareSynthesis

Page 29: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

Cfile

ShapeAnalysis α filepass Termination

Analysis

error

pass

XX

error

XX

BoundsSynthesis

XXfailure

HardwareSynthesis

Page 30: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Hardware synthesis

pass

error

pass

XX

error

XX

XXfailure

α fileShapeAnalysis

TerminationAnalysis

BoundsSynthesis

HardwareSynthesis

Cfile

Page 31: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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α file

failure

Hardware synthesis

ShapeAnalysis

pass TerminationAnalysis

error

pass

error

BoundsSynthesis

XX

XX

Cfile

PreconditionSynthesis

XX

Page 32: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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α file

failure

Hardware synthesis

ShapeAnalysis

pass TerminationAnalysis

error

pass

error

BoundsSynthesis

XX

XX

Cfile

PreconditionSynthesis

XX

Page 33: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Altera DE2 FPGA Board

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Page 34: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Altera synthesis/implementation tools

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Page 35: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Synthesized logic

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Page 36: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

VHDL simulation of prio netlist

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Page 37: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

Logic analyzer output

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Page 38: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Conclusion

Big advances in formal verification, analysis, understanding

Alternative uses for these new techniques? Compiling for embedded systems or hardware? Automatic parallelization? Speculative execution and rollback? Mixed static/dynamic property checking in runtimes? Runtime verification of progress (i.e. termination)?

Current project Solving open problems in hardware synthesis Further blurring the line between hardware and software Demo: first-known synthesis tool supporting dynamic heap

Page 39: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.

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Conclusion

Big advances in formal verification, analysis, understanding

Alternative uses for these new techniques? Compiling for embedded systems or hardware? Automatic parallelization? Speculative execution and rollback? Mixed static/dynamic property checking in runtimes? Runtime verification of progress (i.e. termination)?

Current project Solving open problems in hardware synthesis Further blurring the line between hardware and software Demo: first-known synthesis tool supporting dynamic heap