1Embedded Computer System Laboratory

RTOS Modeling in Electronic System Level Design

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Contents

References

Introduction to RTOS modeling in ESL design

Design Flow

RTOS simulation modelsRTOS interface in SpecC

Difference in SpecC RTOS and SoCOS

Model refinement

Scheduled model

Experimental results

Conclusions

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References

[1] Embedded Software for SoC, chapter 5

[2] RTOS modeling in system level synthesis by Haobo Yu and Daniel Gajski

[3] Operating System based Software Generation for Systems-on-Chip by Dirk Desmet, D. Verkest, and Hugo De Man

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Introduction to RTOS modeling in ESL design

In system-on-a-chip design era, raising the level of abstraction is generally seen as a solution to increase productivity

Timedesign productivity

desig

n com

plexi

ty

System

RTL

ChipSlowest

Fast

Simulation time &

Iteration time

Various system-level design languages have been proposed :

SpecC, SystemC, CynApps, OCAPI, .. etc.

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Introduction to RTOS modeling in ESL design

Dynamic real-time behavior in embedded software can have a large influence on design quality metrics like performance or power

SystemC ver. 3.0 will support real-time OS models.

Specification

Software process Hardware process

Embedded software+ OS

Register transfer Level design

Electronic system level design

Partitioning

Implementation

Design Space Exploration

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Key Issues in ESL RTOS model

Capturing the abstracted RTOS behavior in ESL design

Not requiring any specific language extensions to existing ESL language

Task management

Real-time scheduling

Preemption

Task synchronization

Interrupt handling

Minimal modeling effort

Early and rapid design space exploration

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Design Flow [1],[2]

Processes map to PEs

DynamicStatic

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Design Flow [3] : SoCOS

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RTOS Simulation Models

RTOS Interface in SpecC [1], [2]

Task management

Real-time scheduling

Preemption

Task synchronization

Interrupt handling

Only consider two kinds of tasks :

Periodic hard real time tasks having a critical deadline

Non periodic real time tasks, having a fixed priority

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RTOS Simulation Models

RTOS Interface in SpecC [1], [2] (cont’d)

Specification to Architectural model

Extended RTOS service layer

Process 1

Process 2

PE (processing element)

RTOS interface calls

RTOS channels

task 1 task 2

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RTOS Simulation Models

Difference in SpecC RTOS [1],[2] and SoCOS [3]Consistency in existing ESL libraries

SoCOS requires its own simulation engine

Timing budget vs. estimating execution time

Refinement methodologySoCOS only concerns with communication models (sync/async)

SpecC RTOS uses dynamic scheduling refinement process

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Model Refinement

Task refinement :

behavior-to-task conversion

dynamic child task creation

ready queue

Synchronization refinement :

event handling

event queue

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Scheduled model

Scheduled model (=architectural model) calls the scheduler for selecting a dispatching task from the ready queue

Priority : B3 > B2

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Experimental Result

Example design of a voice codec for mobile phone applicationsContains two tasks; encoding and decoding

Implemented on Motorola DSP56600

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Experimental Result

ADSL modem modeling using SoCOS

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Conclusion

RTOS behaviors are modeled in high level of abstraction.

It allows dynamic real time behaviors to the existing ESL design without much effort

Using RTOS simulation model, early validation and design space exploration can be performed.

Small interfaces of RTOS effectively supports the dynamic behaviors