1

ELEC 422Applied Integrated Circuit

Design

Section 2: MOS Fundamentals

Chuping Liu

[Adapted from Rabaey’s Digital Integrated Circuits, ©2003, J. Rabaey et al., and Gaudet’s lecture notes]

2

Review of

Basic Circuit Theory

OUTLINE

3

Basic Circuit Elements

Resistor (Unit: Ohm)

Heat Dissipater

Capacitor (Unit: Farad)

Charge Storage

Inductor (Unit: Henry)

High Frequency Blocker

4

Resistance of Material

Ohmic Law

Resistors in Series

Resistors in Parallel

Resistance and Ohmic Law

A

LR

+V

I

R

R

VI

3

1111

21 RRRRT

321 RRRRT

5

Capacitance

+V

I

C

Capacitance of Material

Current Behavior

Capacitors in Series

Capacitors in Parallel

L

AC

dt

dVCI

321

1111

CCCCT

321 CCCCT

6

Inductance

+V

I

L

Current Behavior

assuming no mutual interaction,Inductors in Series

Inductors in Parallel

dt

dILV

321

1111

LLLLT

321 LLLLT

7

Kirchhoff’s Law

Voltage For a closed circuit, the total voltage drops at each

elements should add up to the voltage applied to the circuit;

Current For any node in a circuit, the total currents entering

the node should add up to those leaving the node.

8

PN Junction

OUTLINE

9

Silicon

IVA element in periodic table

Four outer shell electrons

Four bonds formed in Si crystal (tetragonal structure)

3D tetragonal structure 2D planar schematic

10

Doping

The intrinsic charge carrier concentrations is very low in silicon (semiconductor), leading to high resistivity, which could not be used in circuit. To increase charge carrier concentrations, doping with impurities is necessary.

For semiconductor, there’re two ways to dope if doped with impurity element P (phosphorus), with 5 outer

shell electrons, the crystal will have excessive electrons, since only 4 electrons of each atom are used to form bonds.

1 phosphorus atom -> 1 free electron n-type

If doped with Al (aluminum, 3 outer shell electrons) -> spare sites for electrons, called holes

1 aluminum atom -> 1 free hole p-type

11

PN Junction

PN junctions consist of two semiconductor regions of opposite type. Such junctions show a pronounced rectifying behavior. They are also called abrupt junction.

The PN junctions are versatile elements. They can be used in the following area: Rectifier, isolation structure and voltage-dependent

capacitor. Solar cells, photodiodes, light emitting diodes and even

laser diodes. Essential part of Metal-Oxide-Silicon Field-Effects-

Transistors (MOSFETs) and Bipolar Junction Transistors (BJTs).

12

PN Junction

p-Si n-Si

Before contact, holes and electrons are evenly distributed in p-Si and n-Si respectively.

hole

still charge

electron

13

PN Junction

p n

after some recombination

diffusion

14

PN Junction

after fully recombination

Depleted Region orSpace Charge Region

p n

diffusion

15

Built-in Potential in Depletion Regionhole diffusion

electron diffusion

p n

hole driftelectron drift

ChargeDensity

Distancex+

-

ElectricalxField

x

PotentialV

W2-W1

(a) Current flow.

(b) Charge density.

(c) Electric field.

(d) Electrostaticpotential.

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Built-in Potential

300Kat mV 26

ln20

q

kT

n

NN

T

i

DAT

0 – the built-in potential T – the thermal voltage NA – the acceptor concentrations in p-materials ND – the donor concentrations in n-materials ni – the intrinsic carrier concentration in a pure sample of

the semiconductor. (≈1.5x1010 cm-3 at 300K for silicon) q – electron charge k – Boltzman constant

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Built-in Potential

Example 3.1 Built-in Voltage of pn-junction

An abrupt junction has doping densities of NA=1015 atoms/cm3, and ND=1016 atom/cm3. Calculate the built-in potential at 300K.

mV638mV1025.2

1010ln26

20

1615

0

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The Diodes

OUTLINE

19

The Diode

n

p

p

n

B A SiO2Al

A

B

Al

A

B

Cross-section of pn-junction in an IC process

One-dimensionalrepresentation diode symbol

Mostly occurring as parasitic element in Digital ICs

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Diode Current – the ideal diode equation

VD

ID = IS(eVD/T – 1)+

–

VD

+

–

+

–VDon

ID

(a) Ideal diode model (b) First-order diode model

IS represents a constant value called the saturation current of the diode.

IS is proportional to the area of the diode, and a function of the doping levels and widths of the neutral regions

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Diode Current – Example 3.2

Assume VS=3V, RS=10kΩ, and IS=0.5x10-16.

VS-RSID=VD

ID=0.224mA, VD=0.757V

ID=0.23mA, VD=0.7V

VS

RS

VD

ID

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Secondary Effects

–25.0 –15.0 –5.0 5.0

VD (V)

–0.1

I D (A

)

0.1

0

0

Avalanche Breakdown

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OUTLINE

The MOS Transistor

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What is a Transistor?

VGS VT

RonS D

A Switch!

|VGS|

An MOS Transistor

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The MOS Transistor Layout

Polysilicon Aluminum

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MOS Transistors - Types and Symbols

D

S

G

D

S

G

G

S

D

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

D

S

G B

NMOS with Bulk Contact

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The NMOS Transistor Cross Section

n areas have been doped with donor ions (arsenic) of concentration ND - electrons are the majority carriers

p areas have been doped with acceptor ions (boron) of concentration NA - holes are the majority carriers

Gate oxide

n+

Source Drain

p substrate

Bulk (Body)

p+ stopper

Field-Oxide(SiO2)n+

Polysilicon Gate

L

W

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Switch Model of NMOS Transistor

Gate

Source(of carriers)

Drain(of carriers)

| VGS |

| VGS | < | VT | | VGS | > | VT |

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)

Ron

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Switch Model of PMOS Transistor

Gate

Source(of carriers)

Drain(of carriers)

| VGS |

| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |

Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)

Ron

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Threshold Voltage Concept

S D

p substrate

B

G VGS +

-

n+n+

depletion region

n channel

The value of VGS where strong inversion occurs is called the threshold voltage, VT

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The Threshold Voltage

VT = VT0 + (|-2F + VSB| - |-2F|)

where

VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process

VSB is the source-bulk voltage

F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon)

is the body-effect coefficient

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The Body Effect

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

-2.5 -2 -1.5 -1 -0.5 0

VSB (V)

VT (

V)

VSB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground)

A negative bias causes VT to increase from 0.45V to 0.85V

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Transistor in Linear Mode

S

D

B

G

n+n+

Assuming VGS > VT and VDS VGS – VT

VGS VDS

ID

x

V(x)- +

The current is a linear function of both VGS and VDS

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Voltage-Current Relation: Linear Mode

For long-channel devices (L > 0.25 micron)

When VDS VGS – VT

ID = k’n W/L [(VGS – VT)VDS – VDS2/2]

where

k’n = nCox = nox/tox = is the process transconductance parameter (n is the carrier mobility (m2/Vsec))

kn = k’n W/L is the gain factor of the device

For small VDS, there is a linear dependence between VDS and ID, hence the name resistive or linear region

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Transistor in Saturation Mode

S

D

B

GVGS

and VDS > VGS - VT

ID

VGS - VT- +n+ n+

Pinch-off

Assuming VGS > VT

VDS

The current remains constant (saturates).

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Voltage-Current Relation: Saturation Mode

For long channel devices

When VDS VGS – VT

ID’ = k’n/2 W/L [(VGS – VT) 2]

since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at VGS – VT

However, the effective length of the conductive channel is modulated by the applied VDS, so

ID = ID’ (1 + VDS)

where is the channel-length modulation (varies with the inverse of the channel length)

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Effects on Current

For a fixed VDS and VGS (> VT), IDS is a function of the distance between the source and drain – L the channel width – W the threshold voltage – VT

the thickness of the SiO2 – tox

the dielectric of the gate insulator (SiO2) – ox

the carrier mobility

- for NMOS: n = 500 cm2/V-sec

- for PMOS: p = 180 cm2/V-sec

ID = k’n W/L [(VGS – VT)VDS – VDS2/2]

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I-V Plot (NMOS)

0

1

2

3

4

5

6

0 0.5 1 1.5 2 2.5

I D (

A)

VDS (V)

X 10-4

VGS = 1.0V

VGS = 1.5V

VGS = 2.0V

VGS = 2.5V

Linear Saturation

VDS = VGS - VT

Qu

adr

atic

de

pe

nde

nce

NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

cut-off

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I-V Plot (PMOS)

-1

-0.8

-0.6

-0.4

-0.2

00-1-2

I D (

A)

VDS (V)

X 10-4

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V

All polarities of all voltages and currents are reversed

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The MOS Current-Source Model

VT0(V) (V0.5) VDSAT(V) k’(A/V2) (V-1)

NMOS 0.43 0.4 0.63 115 x 10-6 0.06

PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1

S D

G

B

ID

ID = 0 for VGS – VT 0

ID = k’ W/L [(VGS – VT)Vmin–Vmin2/2](1+VDS)

for VGS – VT 0 with Vmin = min(VGS – VT, VDS, VDSAT)

Determined by the voltages at the four terminals and a set of five device parameters

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Summary of MOSFET Operating Regions

Strong Inversion VGS > VT

Linear (Resistive) VDS < VDSAT

Saturated (Constant Current) VDS VDSAT

Weak Inversion (Sub-Threshold) VGS VT

Exponential in VGS with linear VDS dependence