EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital...

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EE414 VLSI Design Design Design Metrics in Metrics in VLSI Design apted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Transcript of EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital...

Page 1: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Design Design Metrics in Metrics in

VLSI Design

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

Page 2: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Design Metrics

How to evaluate performance of a digital circuit (gate, block, …)?» Cost» Reliability» Scalability» Speed (delay, operating frequency) » Power dissipation» Energy to perform a function

Page 3: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Design Metrics

34 nm 32 GbFlash memory chip (Intel)

Page 4: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs» design time and effort, mask generation» one-time cost factor

Recurrent costs» silicon processing, packaging, test» proportional to volume» proportional to chip area

Page 5: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

NRE Cost is Increasing

Page 6: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Die Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)

Page 7: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Cost per Transistor

0.00000010.0000001

0.0000010.000001

0.000010.00001

0.00010.0001

0.0010.001

0.010.01

0.10.111

19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012

cost: cost: ¢-per-¢-per-transistortransistor

Fabrication capital cost per transistor (Moore’s law)

Page 8: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Yield

%100per wafer chips ofnumber Total

per wafer chips good of No.Y

yield Dieper wafer Dies

costWafer cost Die

area die2

diameterwafer

area die

diameter/2wafer per wafer Dies

2

Page 9: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Defects

area dieareaunit per defects

1yield die

is approximately 3

4area) (die cost die f

Yield =25% Yield = 83%

Page 10: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Yield Examples (1994)

Chip Metal layers

Line width

Wafer cost

Def./ cm2

Area mm2

Dies/wafer

Yield Die cost

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 601

4 0.80 $1700 1.3 121 115 28% $53

HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

Page 11: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Example You want to start a company to build a

wireless communications chip. How much venture capital must you raise?

Because you are smarter than everyone else, you can get away with a small team in just two years:» Seven digital designers» Three analog designers» Five support personnel

From lecture : Scaling and Economics by David Harris

Page 12: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Solution Digital designers:

» $70k salary

» $30k overhead

» $10k computer

» $10k CAD tools

» Total: $120k * 7 = $840k Analog designers

» $100k salary

» $30k overhead

» $10k computer

» $100k CAD tools

» Total: $240k * 3 = $720k

Support staff» $45k salary

» $20k overhead

» $5k computer

» Total: $70k * 5 = $350k Fabrication

» Back-end tools: $1M

» Masks: $1M

» Total: $2M / year Summary

» 2 years @ $3.91M / year» $8M design & prototype

From lecture : Scaling and Economics by David Harris

Page 13: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Reliability―Noise in Digital Integrated Circuits

VDDv(t)

i(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power andground noise

Page 14: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

DC OperationVoltage Transfer Characteristic

V(x)

V(y)

VOH

VOL

VM

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

Page 15: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Mapping between analog and digital signals

"1"

"0"

VOH

VIH

VIL

VOL

UndefinedRegion

V(x)

V(y)

VOH

VOL

VIH

VIL

Slope = -1

Slope = -1

Page 16: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Definition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

Page 17: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Noise Budget

Allocates gross noise margin to expected sources of noise

Differentiate between fixed and proportional noise sources

Sources: supply noise, cross talk, interference, offset

Shielding: metal lines and guard rings used to lower signal interference

Page 18: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Key Reliability Properties

Absolute noise margin values are deceptive» a floating node is more easily disturbed than a

node driven by a low impedance (in terms of voltage)

Noise immunity is the more important metric – the capability to suppress noise sources

Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;

Page 19: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Regenerative Property

in

out out

in

f(v)

finv(v)

finv (v)

f(v)

v3

v1

v2 v0v0 v2

v3

v1

Regenerative Non-Regenerative

Page 20: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Regenerative Property

(a) A chain of inverters

v0 v1 v2 v3 v4v5 v6

…

0 2 4 6 8 10t (nsec)

–1

1

3

5

V (V

olt)

v0

v1 v2

(b) Simulated response of chain of MOS inverters

Page 21: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Fan-in and Fan-out

•Fan-out:•Number of load gates, N, that are connected to the output of the driving gate•tends to lower the logic levels•deteriorates dynamic performance•gate must have low output resistance to drive load•library cells have maximum fan-out specification

•Fan-in:•Number of inputs, M, to the gate•large fan-in gates are more complex•results in inferior static and dynamic performance

Page 22: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Fan-in and Fan-out

N

M

(a) Fan-out N

(b) Fan-in M

Page 23: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

The Ideal Gate

Vin

Vout

g=

Ri =

Ro = 0

Fanout =

NMH = NML = VDD/2

Characteristics

Page 24: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

An Old-time Inverter

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

1.0

2.0

3.0

4.0

5.0V

out (

V)

VMNMH

NML

Page 25: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Delay Definitions

t

Vout

t

Vin

50%

50%

10%

90%

tpLHtpHL

trtf

Page 26: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Ring Oscillator

T = 2 tp N

v0 v1 v2 v3 v4 v5

v0 v1 v3

tp

VDD/2

VDD

v5

Page 27: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

A First-Order RC Network

vout

vin C

R

tp = ln (2) = 0.69 RC

Important model – matches delay of inverter

Page 28: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Power Dissipation

Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power: Ppeak = Vsupplyipeak

Average power:

Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1

Page 29: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav tp

Energy-Delay Product (EDP) =

quality metric of gate = E tp

Page 30: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

A First-Order RC NetworkVdd

Vout

isupply

CL

E0->1 = CLVdd2

PMOS

NETWORK

NMOS

A1

AN

NETWORK

E0 1 P t dt

0

T Vdd isupply t dt

0

T Vdd CLdVout

0

Vdd

CL Vdd 2= = = =

Ecap Pcap t dt

0

T Vouticap t dt

0

T CLVoutdVout

0

Vdd 1

2---C

LVdd

2= = = =

vout

vin CL

R

Page 31: EE414 VLSI Design Design Metrics in Design Metrics in VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE414 VLSI Design

Summary

Digital integrated circuits have come a long way and still have some potential left for the coming decades

Some interesting challenges ahead» Getting a clear perspective on the challenges and

potential solutions » Understanding the design metrics that govern

digital design is crucial» Optimize the design metrics - cost, reliability,

speed, power and energy dissipation


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