06/05/08

Biscotti: a Framework forToken-Flow based

Asynchronous Systems

Charlie Brej

06/05/08

Overview

The tool problem

Proposed system

Biscotti components

Their current state

Example uses

Conclusions

And future work

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The Tool Problem

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Wagging Flow ProblemTLF

Read

Async Trans.Desynchronise

NetlistFlatten

TimingLibrary

TimingExtract

NetlistFlatten

VerilogWrite

SimulationPerformance

VerilogRead

Async Trans.Wag

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Commercial Tools

Unsuitable

Critical path extraction

Broken

Timing extraction of cyclic designs

Inflexible

Limited simulation trace extraction

Unimplemented

DI logic synthesis

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Biscotti Aims

Complete framework for token flow systems

Aims to recreate all tools required to make a design

Modular

Set of libraries

Open Source

GPLv3

Expandable and Customisable

Trivial to add or replace any part with own version

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Current Biscotti Components

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Parts

Verilog TLF

Verilog SDF

SimulationNetlist

Operations

Timing Wagging

Async Transformations

Tech-map

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Input

Verilog

Modules, Gates

UDPs with MVL extensions

No behavioral

TLF

Cell characterisations

Splines

In: Capacitance and Slew

Out: Delay and Slew

primitive trinary_C(Z,A,B); output Z; input A, B; reg Z; table

// A B : Z : Z’ 0 0 : ? : 0; 1 1 : ? : 1; 2 2 : ? : 2; ? ? : ? : -; endtableendprimitive

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Output Verilog

Patchy

Generates verilog executable with NC-Verilog

SDF

Timing extraction files used by external simulators

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Processing 1 Netlist Operations

Internal netlist representation

Allows constructing, altering, flattening...

The basis of all other tools

Timing

Cell timing characteristics (TLF)

Circuit timing extraction

Characterisation of constructed modules

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Processing 2

Pipeline Synthesis

Takes a directed flow graph (DFG) style circuit

Constructs latches and acknowledge trees

Can expand to early output, DIMS or MVL

Creates RAM wrappers and wagging fork/join blocks

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C

Pipeline Synthesis

LogicAsyncLogic Async

Latch

AsyncLatch

AsyncLatch

AsyncLatch

AsyncLatch

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Processing 2

Pipeline Synthesis

Takes a directed flow graph (DFG) style circuit

Constructs latches and acknowledge trees

Can expand to early output, DIMS or MVL

Creates RAM wrappers and wagging fork/join blocks

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Processing 3

Wagging

Duplicates circuit and reconnects latches to form a ring

Inserts abstract fork/join blocks Simulation

Fast simulator

Slowest trace extraction

MVL capable

Allows simulation at an abstract level

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Processing 4

Tech mapping

Dumb generation of large primitives (balanced trees)

Table based re-synthesis of C-element blocks

Logic blocks in the future

Slowest trace based gate replacement (drive strength)

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Example Uses

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Timing extraction

VerilogRead

TLFRead

NetlistFlatten

TimingExtract

VerilogWrite

SDFWrite

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Extract Slowest PathVerilogRead

TLFRead

NetlistFlatten

TimingExtract

SimulationSlowest Trace

Slowest PathWrite

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Drive Strength OptimisationVerilogRead

TLFRead

NetlistFlatten

TimingExtract

SimulationSlowest Trace

Tech-mapFind Better Cell

NetlistReplace Element

VerilogWrite

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Large C-element generationVerilogRead

TLFRead

Async TransC-element Gen

TimingExtract

Tech-mapFind Better Cell

VerilogWrite

TimingGenerate Splines

TLFWrite

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Conclusions

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Current state

Pre-alpha

Pretty unusable

Used to generate RedStar

Parts implemented when needed

About 6 months from public beta

Currently available on request

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Future Work

Implement RedStar using system

Using as few commercial tools as possible

Example design

Complete system back-end components

Implement front-end

Scripting of operations

GUI

Benchmark suite

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Biscotti Conclusions

Allows implementation of asynchronous designs

Without relying on commercial tools

Tools suited to asynchronous designs

Easy expansion

Allows rapid evaluation of researched techniques

Fairly compare to existing methods

Useful analysis techniques

Still incomplete

06/05/08

Thank you