05 - combinational building blocks

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Digital Circuits I

Combinational Building Blocks

University of the PhilippinesElectrical and Electronics Engineering Institute

2Joy Reyes-Madamba@2010

Typical Building Blocks

�Adders

�Magnitude Comparators

�Decoders

�Encoders

�Multiplexers

�Demultiplexers

�Array Logic

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Binary Addition

0 1 1 0

0 0 1 1

0 1 10 1

+ + + +

Carry-OutSum



Half-Adder

A

CO

S

B

Carry Out

Sum

AB Result

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Carry Out = Co = AB

Sum = S = A’B + AB’

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Half-Adder Implementation



Implementing Bit-wise Addition

Separately

B1

C0

S0

B0A1

C1

S1

A0

Half adder to add LSB

Half adder to add MSB

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Implementing Bit-wise Addition

Separately

B1

C0

S0

B0A1

C1

S1

A0

Result = C1S1S0

where C1=MSB

and S0=LSB



Example (1/2)

Let A1A0 = 10

B1B0 = 10

Then C0 = 0

S0 = 0

C1 = 1

S1 = 0

C1S1S0 = 100

B1

C0

S0

B0A1

C1

S1

A0

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Example (2/2)

Let A1A0 = 01

B1B0 = 01

Then C0 = 1

S0 = 0

C1 = 0

S1 = 0

C1S1S0 = 000 X

B1

C0

S0

B0A1

C1

S1

A0



Full-Adder (1-bit) (1/2)

A1B1C0 C1S1

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Carry In Carry Out

Carry Out = C1

= A1B1+B1C0+A1C0

Sum = S1 = A1 ⊕ B1 ⊕ C0

C0

A1

+ B1

C1S1

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Full-Adder (1-bit) (2/2)



Full-Adder Implementations (1/3)

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S = z ⊕ (x ⊕ y) = z’(xy’ + x’y) + z(xy’ + x’y)’

= z’(xy’ + x’y) + z(xy +x’y’) = xy’z’ + x’yz’ + xyz + x’y’z

C = z(xy’ + x’y) + xy = xy’z + x’yz + xy




CIN

COUT

A

S

B

Full

Adder

A B CIN

S0COUT

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n-Bit Full-Adder w/ Ripple Carry (1/2)

�The carry-out in the addition of the previous bit is

forwarded to be the carry-in in the addition of the

current bit.

C2 C1 C0

A3 A2 A1

+ B3 B2 B1

C3 S3 S2 S1



n-Bit Full-Adder w/ Ripple Carry (2/2)

Full

Adder

A0B0 CIN.0

S0COUT.0

Full

Adder

A1B1 CIN.1

S1COUT.1

Full

Adder

A2B2 CIN.2

S2COUT.2

Full

Adder

A3B3 CIN.3

S3COUT.3

0

Result = COUT.3 S3 S2 S1 S0

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� Use a sign bit

� Use 1’s complement notation

� Use 2’s complement notation

Subtraction

6 6

5 (-5)

1 1

- +

How do you express negative binary numbers?



Sign Bit

-5 = ?

-5 using a

sign bit

Append extra

sign bit in front:

0 if positive,

1 if negative

5 = 0101

10101

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1’s Complement

Simply complement

all the bits of the

binary representation

of the equivalent

positive number.

Note: After doing addition, add any carry-out bit back to the sum.

-5 = ?

-5 in 1’s

complement

notation

5 = 0101

1010



Example

6

(-5)

1

+ Sum = 0000

Carry-out = 1

0000

1

0001

+Answer = 1

+

111

0110

1010

10000

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2’s Complement

Simply complement all

the bits of the binary

representation of the

equivalent positive

number, then add 1.

-5 in 2’s complement notation

+

-5 = ? 5 = 0101

1010

1

1011



Example

111

6 0110

(-5) 1011

1 10001

++Sum = 0001

Carry-out = 1

0001 Answer = 1

Note: Maintain the same number of bits.

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Controlled Inverter (1/2)

A B Y A B Y A B Y

0 0 0 0 0 0 A 0 A

0 1 1 1 0 1 A 1 A'

1 0 1 0 1 1

1 1 0 1 1 0

YA

B Control Input



Controlled Inverter (2/2)

�View input B as a control unit that allows A to

pass through unchanged when B=0, and inverts A

when B=1

A3 A2 A1 A0

B

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Full-Adder and Subtractor

� A+B when Add/Sub =

0

� A+(-B) when Add/Sub

= carry-in = 1

B0

Add/

Sub

B1

F.A.

A0A1

F.A.

S0S1

C0C1

(Cin )

Cout



Recall: Full-Adder Circuit

CIN

COUT

A

S

B

Full

Adder

A B CIN

S0COUT

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4-bit Adder-Subtractor

When M=0, acts as an adder

When M=1, acts as a subtractor

C indicates carry, V indicates overflow



Non-Ideal Conditions (1/2)

� Each gate will have an

inherent delay before it

outputs the correct value

� This delay is directly

proportional to the

number of levels of

gates traversed

CIN

COUT

A

S

B

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Non-Ideal Conditions (2/2)

COUT will be valid after

two gate delays.

S will be valid after one

gate delay.

CIN

COUT

A

S

B



n-Bit Full-Adder w/ Ripple Carry

Full

Adder

A0B0 CIN.0

S0COUT.0

Full

Adder

A1B1 CIN.1

S1COUT.1

Full

Adder

A2B2 CIN.2

S2COUT.2

Full

Adder

A3B3 CIN.3

S3COUT.3

0

(Slow circuit) Signal must propagate through the gates before

correct result of n-bit addition is available at the output terminals.

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Carry Look-Ahead (1/4)

�Express each carry-out bit in terms of the inputs

only.

�Build a circuit (carry look-ahead generator) that

will compute for all the needed carry-ins at the

same time.




Recall that COUT =AB + BCIN + ACIN and S= A ⊕ B ⊕ CIN

For n-bit addition,

S0= A0 ⊕ B0 ⊕ CIN0

S1= A1 ⊕ B1 ⊕ CIN1

…

Sn= An ⊕ Bn ⊕ CINn

EEE 8 Course Notes, Third Long Exam

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For n-bit addition,

COUT = AB + BCIN + ACIN = AB + (A+B)CIN

COUT1 = A1 B1+(A1+B1)CIN1

COUT2 = A2 B2+(A2+B2)CIN2

but CIN2 = COUT1, so substituting

COUT2 = A2 B2+(A2+B2)[A1 B1+(A1+B1)CIN1]

0




COUT2 = A2 B2+(A2+B2)[A1 B1+(A1+B1)CIN1]

(change variables)

= G2+P2(G1+P1G0)

= G2+G1P2+G0P2P1

COUT3 = A3B3 + (A3+B3) [G2+G1P2+G0P2P1 ]

COUT3 = G3+G2P3+G1P3P2+G0P3P2P1

…

COUTn= Gn+1+Gn + Gn-1Pn +…+ G0PnPn-1 … P1

G = AB (generate)

P = A+B (propagate)

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Recall: Full-Adder Circuit



Carry Look-

Ahead

Generator

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37Joy Reyes-Madamba@2010EEE 8 Course Notes, Third Long Exam

4-Bit Adder with

Carry Look-

Ahead



Magnitude Comparator

�A circuit that compares two binary numbers, and

determines their relative magnitudes

A B A < B A = B A > B

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

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4-Bit Magnitude Comparator

A3

A2

A1

A0

B3

B2

B1

B0

A>BA=B

A<BThe output at this

pin=1 if A>B



4-Bit Magnitude

Comparator

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Magnitude Comparators

�To compare 2 eight-

bit numbers: use

comparators in

cascade

A7

A6

A5

A4

B7

B6

B5

B4

> = <

> = <

> = <

> = <

‘0’ ‘1’ ‘0’

A3

A2

A1

A0

B3

B2

B1

B0

A>B

A=B A<B



Decoders (1/2)

�MSI combinational circuits that convert or decode

binary information from n input lines to a

maximum of 2n unique output lines (usually the 2n

minterms of n input variables).

.

.

.

.

.

.N inputs 2N outputs

Nx2N Decoder

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Decoders (2/2)

�Decoder size is specified in terms of having (n

inputs by m outputs), where max(m)=2n

�An n-bit binary input {Xn-1Xn-2…X0} will assert the

mth output line, where m is the decimal

equivalent of n.

�Only one output line will be asserted at any given

time.



2-to-4 Decoder

A1 A0 W X Y Z

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

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W = A1' A0'

X = A1' A0

Y = A1 A0'

Z = A1 A0

A0A1

2-to-4 Decoder Implementation



3-to-8 Decoder Implementation

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Enable Input

�The decoder has an enable input line that allows

the decoder to accept or ignore data inputs

D0

D1

En

2x4 Decoder

Y0

Y1

Y2

Y3

En D1 D0 Y0 Y1 Y2 Y3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1



Implementing Functions Using

Decoders

�Select the output lines of the decoder that

correspond to the minterms of the function to be

implemented.

�Connect these chosen output lines to the inputs of

an OR gate.

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Example (1/2)

�Implement the full-adder

using a decoder and the

necessary logic gates

A1B1C0 C1S1

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1



Example (2/2)

A1

B1

C0

S1

C1

3X8

Decoder

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1-to-2 Decoder as Inverter

A F

0 1

1 0

FA

FY0

Y1

A D0

Note: these labels are

used to indicate the

order of significance of

these lines. Each output

line corresponds to a

possible minterm. To

implement a function,

choose the output lines

that must be asserted.



2-to-4 Decoder as XOR Gate

A B F

0 0 0

0 1 1

1 0 1

1 1 0

FA

B

Y0

Y1

Y2

Y3

D1

D0

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Interconnecting Decoders

�Decoder circuits can be connected together to

form a larger decoder circuit

�The number of decoders needed can be

determined by comparing the number of input and

output pins of the available decoder with that of

the desired decoder.



Example (1/3)

�Construct a 4x16 decoder using only 3x8

decoders with enable inputs

# lines Required decoder Available decoder # needed decoders

input 4 3 2output 16 8 2

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Example (2/3)

3x8

3x8

E

E

A

B

C

D

D0

D7

D8

D15

MSB

MSB



Example (3/3)

�Construct a 6x64 decoder using only 3x8

decoders with enable inputs

# lines Required decoder Available decoder # needed decoders

input 6 3 ?output 64 8 ?

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BCD-to-7 Segment Decoders (1/2)

a

b

c

d

e

f g

h

�Each segment is

composed of a light

emitting diode.

�In order to display letters

or numbers, the

corresponding segments

should be activated.



BCD-to-7 Segment Decoders (2/2)

/LT D C B A a b c d e f g

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 1 1 0 0 1 1 1 1

1 0 0 1 0 0 0 1 0 0 1 0

1 0 0 1 1 0 0 0 0 1 1 0

1 0 1 0 0 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0 0 1 0 0

1 0 1 1 0 1 1 0 0 0 0 0

1 0 1 1 1 0 0 0 1 1 1 1

1 1 0 0 0 0 0 0 0 0 0 0

1 1 0 0 1 0 0 0 1 1 0 0

0 x x x x 0 0 0 0 0 0 0

D

C

B

A

/LT

a

b

c

d

e

f

g

h

( BCD = Binary Coded Decimal )

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Encoders

�Circuits that generate the binary code for the 2n

input variables

AB

2N inputsN outputs



4-to-2 Encoder

I3 I2 I1 I0 OUT1 OUT0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Out0

Out1

I0

I1

I2

I3

Assume that only one

input is asserted

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Priority Encoders

I3 I2 I1 I0 OUT1 OUT0

0 0 0 1 0 0

0 0 1 X 0 1

0 1 X X 1 0

1 X X X 1 1

Out0

Out1

I0

I1

I2

I3

Assume that at least

one input is

asserted



Multiplexer (Mux)

�Circuit that selects binary information from one of

many input lines and directs it to a single output

line.

n-to-1 Mux

n inputs 1 output

m control

n = 2m input lines,

m select lines,

only 1 output line

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2-to-1 Multiplexer

A B S C

0 X 0 0

1 X 0 1

X 0 1 0

X 1 1 1

C = AS’ + BS

A

B

S

C



2-to-1 Multiplexer Implementation

A

S

B

C

AS'

BS

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4-to-1 Multiplexer

A

B

C

D

S0

S1

E

S1S0 E

00 A

01 B

10 C

11 D




Multiplexers (1/2)

�Multiplexers can be used to implement truth

tables.

� The input variables are directly connected to the

select lines of the multiplexer. The minterms that give

a logic 1 output have their input lines equal to 1 while

the rest have their input lines connected to 0.

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Multiplexers (2/2)

�We can also use a 2n-to-1 multiplexer to

implement a truth table with n+1 variables.

� The n variables are connected to the n select lines

while the remaining single variable is used for the

inputs of the multiplexer.



Example 1

A B C D

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

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Example 2 (1/3)

�Implement this truth table

using a 4-to-1 multiplexer.

�Let us choose C as the one to

be connected to the input

lines, and A and B to the

select lines of the multiplexer.

A B C D

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0



Example 2 (2/3)

A B C D

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

D=0

D=1

D=C

D=C’

�Divide the truth table into

sections, with each section

having identical values of A

and B

�Express the output in terms

of C, 1 or 0

�Use C, C’, 1 or 1 as data

inputs of the multiplexer

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Example 2 (3/3)



Choosing a different variable

B C A D

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0

D=A

D=1

D=A’

D=0

�If we choose a different

variable, we have to

rearrange the truth table

accordingly

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Demultiplexers

�Circuits that direct binary information from a single

input line to one of 2n possible output lines. The

output line is selected using n selection or control

lines.

m = 2n output lines,

n control lines,

only 1 input line1-to-m Demux

n control

1 input m outputs



1-to-4 Demultiplexer

D S0 S1 f1 f2 f3 f4

0 0 0 0 0 0 0

0 0 1 0 0 0 0

0 1 0 0 0 0 0

0 1 1 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

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Decoder/Demultiplexer (1/2)

�Decoder with Enable input line and Demultiplexer are

essentially the same

D0

D1

En

2x4 Decoder

Y0

Y1

Y2

Y3

Use as

select lines

Use as

input line



Decoder/Demultiplexer (2/2)

En D1 D0 Y0 Y1 Y2 Y3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

Decoder

Demux

D S0 S1 f1 f2 f3 f4

0 0 0 0 0 0 0

0 0 1 0 0 0 0

0 1 0 0 0 0 0

0 1 1 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

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Combinational Building Blocks

Encoder

Decoder

n inputs

m inputs

m outputs

n outputs

Multiplexer

n inputs 1 output

Demultiplexer

m control

n control

1 input m outputs



Combinational Programmable

Logic Devices (PLD)

Three Basic Types of PLDs:

�ROM (Read-Only Memory)

�PLA (Programmable Logic Array)

�PAL (Programmed Array Logic)

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Basic Configuration



Why Use Array Logic?

�Blocks can be programmed for customized

applications

�Ideal for implementing large multiple-output

systems

�Reduce device count and board size

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Read-Only Memory (ROM) (1/3)

�This is a device that incorporates a decoder and a

programmable array of OR gates.

�Connections between decoder outputs and inputs

of OR gates are specified by “programming” the

ROM.

�ROMs come with special internal links that can be

fused or broken. (Total #ROM links = 2n x m)




2n x m ROM

n

inputs

m outputs: f1 fm

n-to-2n

decoder

address

word

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� n inputs result in 2n decoder outputs connected to

m OR gates to produce m outputs or functions

�Each bit combination of the input variables is

called an address

�Each bit combination that comes out of the output

lines is called a word



Example (1/2)

�Implement the following truth table using a 4x2

ROM.

A1 A0 F1 F2

0 0 0 1

0 1 1 0

1 0 1 1

1 1 1 0

If ROM size is 4x2, then

inside it will have a 2-

to-4 decoder and 2 OR

gates

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4 x 2 ROM

A0

A1

F1 F2

D0

D1

D2

D3

Example (2/2)



Types of ROMs

� Custom-masked ROM – done by the manufacturer, design submitted by customer; costly

� Programmable ROM (PROM) – may be programmed once by the customer

� Erasable PROM (EPROM) – can be reprogrammed by the user; can be erased using ultraviolet light

� Electrically erasable PROM (EEPROM) – uses electrical signals to erase

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Applications of ROMs

Implement complex combinational circuit directly

from their truth tables

�Code converters – e.g. ASCII to EBCDIC

�Arithmetic functions – e.g. multipliers

�Display of characters in a cathode-ray tube

�Control units – e.g. BIOS



Conventional and Array Logic

Diagrams

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5x8 ROM



Programming the ROM

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Programmable Logic Array (PLA) (1/2)

�A PLA is similar to a ROM in concept, but does

not provide full decoding of the variables and

does not generate all the minterms.

�PLA retains the programmable OR array, but the

decoder inside is replaced by a group of AND

gates, each of which can be programmed to

generate a product term of the input variables.



Programmable Logic Array (2/2)

�The specific Boolean functions are implemented

in sum-of-products form by opening appropriate

links and leaving the desired connections.

�Links are provided over output inverters such that

the output function can be generated in either the

AND-OR form or in the AND-OR-NOT form.

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PLA Block Diagram (1/2)



n

inputs

m

outputs

f1

f2

n x 2n Decoder

2n x m PLA

n

inputs

m

outputs

f1

f2

PLA Block Diagram (2/2)

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Example (1/2)

�Implement this truth table using a PLA

A B C F1 F2

0 0 0 0 0

0 0 1 0 0

0 1 0 0 0

0 1 1 0 1

1 0 0 1 0

1 0 1 1 1

1 1 0 0 0

1 1 1 1 1



A

B

C

PLA

m

outputs

f1

f2

Example (2/2)

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PLA Programming (1/3)

1. Determine the minimal SOP form

of the functions.




2. Create the PLA program table

F1 = AB’ + AC

F2 = AC + BC

Product

term A B C F1 F2

AB' 1 1 0 - 1 -

AC 2 1 - 1 1 1

BC 3 - 1 1 - 1

T T T/C

Inputs Outputs

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3. Draw the PLA fuse map

PLA with 3 inputs, 3 product terms and 2 outputs



Example (1/2)Given:

F1 (A,B,C) = Σ(3,5,6,7) F2 (A,B,C) = Σ(0,2,4, 7)

Using map simplification,

F1 = AC + AB + BC

F1’ = B’C’ + A’C’ + A’B

F2 = B’C’ + A’C’ + ABC

F2’ = B’C + A’C + ABC

The combination with the minimum number of product terms:

F1 = (B’C’ + A’C’ + A’B)’

F2 = B’C’ + A’C’ + ABC

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Example (2/2)

F1 = (B’C’ + A’C’ + A’B)’

F2 = B’C’ + A’C’ + ABC

Product

term A B C F1 F2

B'C' 1 - 0 0 1 1

A'C' 2 0 - 0 1 1

A'B' 3 0 0 - 1 -

ABC 4 1 1 1 - 1

C T T/C

Inputs Outputs



Programmed Array Logic (PAL) (1/2)

�A PAL is a device that incorporates a

programmable AND array with a fixed OR array

�AND gates are connected to OR gates in a fixed

position with no overlap (no AND gate can be

used in more than one function)

�Seldom used to realize large numbers of functions

of exactly the same large set of variables

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A

B

C

PAL

m

outputs

f1

f2

Programmed Array Logic (2/2)



PAL with 4

inputs, 4

outputs, and

Three-wide

AND-OR

structure

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PAL Programming (1/2)

Consider the following Boolean functions:

w(A,B,C,D) = Σm(2,12,13)

x(A,B,C,D) = Σm(7,8,9,10,11,12,13,14,15)

y(A,B,C,D) = Σm(0,2,3,4,5,6,7,8,10,11,15)

z(A,B,C,D) = Σm(1,2,8,12,13)



PAL Programming (2/2)

Simplifying,

w = ABC’ + A’B’CD’

x = A + BCD

y = A’B + CD + B’D’

z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D

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PAL

Programming

Table



PAL

Fuse Map

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Summary of Array Logic

AND Array OR Array

ROM fixed programmable

PLA programmable programmable

PAL programmable fixed

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