Post on 22-Oct-2014
80186 has integrated interface units like Priority Controller,
Programmable Timer,DMA controller and address decoding circuit. It is mostly used in industrial control circuits 80286-enhancement of 8086-16 bit with no integrated peripherals. It
has Virtual memory management circuit, protection circuit and 16 Mbyte addressing capacitySupport multiuser 80386 - 32 bit -4 Gb memory each segment size up to 4GB.improved
memory management . 80486- same as 80386.main feature include build-in-8 Kbyte code/data
cache & 32 bit floating point unit
Multi user /Multi tasking is achieved by time sharing Below we discuss the major problems encountered in
building multi tasking operating system Terminate and stay resident (TSR) Preserving the Environment Accessing the Resources The need for protection
Terminate and Stay Resident (TSR) is a computer system
call in DOS computer operating systems that returns control to the system as if the program has quit, but keeps the program in memory
Time-Slice Scheduling Preemptive Priority based scheduling
Preserving Environment: The Register , data, pointer etc
used by an executing task are referred as environment. Separate Stack or special segment are used to store these data.
Accessing resource: Managing the common resources
using semaphore or flags. Data protection: Global data used by many task are need to control. the segment which must be protected is called critical region.
Memory Management Overlays Bank Switching Virtual memory and Memory Management Units
Eg for overlay
Virtual Memory Hard disk is added to the Memory Hierarchy . Hard disk become main program and data memory The DRAM function as intermediate cache and SRAM
acts as high speed cache for the DRAM In a virtual memory system the code and data segments loaded from the disk Segments which are not in the DRAM are loaded from disk If DRAM is full,one segment in DRAM is swapped out to the disk to make room for swapping in segment
There are 3 different types of loading and swapping of
code and data 1. Segments (64 K bytes) 2. Small Page (4K bytes) 3. Segment paging Virtual memory can be managed by OS but most of
the system use hard ware device called MEMORY MANAGEMENT UNIT(MMU)
Usually in assembly level language address are
referred by logical address For eg JNZ Label Label denotes the logical address, which is represented by Base address and offset.BIU produces the physical memory address.
In 80286 when a program is compiled with an
MMU,logical address or virtual address are represented by two components 16 bit segment selector lower components is offset MMU uses this segment selector to access a descriptor table. Descriptor is a table which contains a series of segment memory location which contains physical base address of the segment.
The selector have 14 address bits and 2 privilage level
bits Since 14 address bits there are 16,384 descriptors in the descriptor table It have the virtual address space accessible upto 1 Gbytes
Features of 80286 High performance processor Large address space (16 Mb physical and 1 Gb virtual
memory) Integrated MMU, Memory protection, Virtual memory support Upward compatible modes Real mode & Protected mode 16 bit data bus 24 bit non multiplexed address bus Packaged in 68-pin ceramic pack
Architecture
Four separate units Address unit Execution unit Bus unit
Instruction unit
24 address pins 16 data pins BHE, Status(S0,S1 and M/IO) HOLD,HLDA,INTRA,INTA,NMI,READY,LOCK and RESET
functions basically as 8086 Four pins used to interface with the coprocessors such as
MATH coprocessor PEREQ(processor extension request)-used by coprocessor to signal the 80286 to do data transfer from memory for it.
PEACK- processor extension acknowledge signal the
start of data transfer for co processor BUSY- function same as TEST signal in 8086 ERROR-asserted by the coprocessor when it finds some error
Register Set
Flag Register
Machine Status Word
MP-Monitor Processor Extension if set,allows the WAIT instruction to
generate processor extension not present exception PE-Protection Enable-enables 80286 in protected mode. EM-Emulate Processor Extension- if set causes a processor extension absent exception & permit processor emulation TS Task Switch-if set, indicates next instruction will rise exception 7.CPU test the current processor extension is for current task
Real Addressing Modes & Protected Addressing Mode Memory is organized into logical segments. Segment
size can be anywhere between 1 Byte to 64 KByte.
Each segment has a descriptor. Descriptor is a block of contiguous memory location
containing information of a segment like segment base address, segment limit, segment type, privilege level, descriptor type ,segment availability and segment used by another task1.
2.
Segment Descriptor (Code, Data and Stack) System control Descriptor (System data & control transfer operation)
Format of the descriptor
System Segment Descriptor Used to store system data and execution state of a task There are 7 types of s/m descriptors Type 1-3 are called as system descriptors
Type 4-7 are called as gate descriptors (used to control
the entry points with in the code to be executed)
Bit Definition
Gate Descriptor It controls the access to entry points of the code to be
executed ,contains information about destination control transfer, required stack manipulations, privilege level and its types There are 4 types of gate descriptors 1. call gate (used to alter privilege level) 2. task gate (used to switch one task to another) 3. interrupt gate 4. trap gate (3 & 4 used to specify corresponding service routine)
Gate Descriptor
Bit definition of gate descriptor
Segment Descriptor Cache Registers A 6 byte segment descriptor cache register is assigned
to each of the 4 segments (CS,DS,SS and ES) A segment descriptor is automatically loaded in a segment descriptor cache register, when ever a associated segment register is loaded with a selector
Descriptor Cache Register format
Selector Fields In the protected mode the content of segment
registers are know as Selector
0-1 indicates the selector privilege level desired
Privilege requested level (PRL) 2 Table Indicator (local or global) 3-15 -index
Privilege 4 levels of privilege mechanism to access the descriptor
A transition from an outer ring to an inner ring is
made possible by using a special control-structure (known as a call gate) A transition from an inner ring to an outer ring is not nearly so strictly controlled Task Privilege-each task has its priority or privilege at
any four levels Task privilege level at that instant is called as Current Privilege Level. It is defined lower order two bits of CS register
Descriptor privilege-Specified by DPL field It specifies the least privilege level used to refer the
descriptor Selector Privilege specified by RPL field of selector RPL is used to ensure that the pointer parameters
passed to a more privilege procedure are not given access of data at privilege higher than the caller routine
Protection : 3 Basic mechanismRestricted use of segments-achieved with the help of read/write privilege 2. Restricted Access to Segment- achieved with the help of DPL 3. Privileged Instruction or operations-executed by based on privilege levels determined by CPL and I/O privilege level defined by the flag register1.
Bus Operation 80286 provides set of signals to interface the memory
and i/o devices 82288 derives control signal from the 80286 to encode the bus cycles Memory is organized as even and odd banks of memory(A0 & BHE are used to address the banks) 80286 divides input clock freq by two to derive PCLK
Basic Six operationsI/O read, I/O write Memory read, Memory write
Interrupt Ack & Halt
At any instance 80286 has 4 states 1. Idle State(Ti) 2. Perform Command State (Tc) 3. Send Status State(Ts) 4. Hold State (TH)
Basic Bus Cycle-Read Read Cycle
Use of CMDLY to Control Command Signal
Fetch Cycles 80286 implements pipelined fetching of instruction Theses perfected instruction are stored in a 6 byte
queue, from where the decoding and execution happens It fetches two bytes of code at a time sequentially In case of branch type instruction ,the prefecthing stops and the queue is flushed Other wise prefetch happens till the HLT instruction