80286 MICROPROCESSOR

Prepared By:- Prof. Jorvekar G.N.HOD Computer

KVN NAIK SP SANSTHA’S POLYTECHNIC,NASHIK

Features• High performance 16-bit microprocessor

chip on-chip memory protection capabilities that supports multitasking.

• Has 16-bit data bus and 24-bit non multiplexed address bus.

• Can address 16 mb (224) of physical memory and 1 gb(230) of virtual memory per task.

• Can be operated in three different clock speed- 4mhz,6mhz,8mhz.

• The 80286’s performance is upto 6 times faster than standard 5-mhz 8086.

• 80286 is housed in a 68-pin leadless flat package.

• It contains four separate processing units.• It can work in two different modes-

real address modeProtected virtual address mode.

• Includes special instructions to support operating system.

Architecture

• 80286 contains 4 separate units-:

Bus unit:-

1) Performs all memory and i/o read and

writes,

2) prefetches instruction bytes,

3) And controls transfer of data to and from

processor extension devices.

Instruction Unit(IU):-

Fully decodes up to three prefetched instructions and holds them in a queue, where the execution unit can access them. This is an implementation of pipelining instead of “waiting to finish one instruction before fetching the next” method.

Execution Unit (EU):-

It uses the 16-bit ALU to execute instructions it receives from the Instruction Unit.

When operating in real mode, 80286 register set is similar to that of 8086 except for a 16-bit machine status word(msw) register.

Address Unit ( AU ):- 1) It computes the physical address. 2) In real mode- uses segment base and

offset. Same ds,es,cs,ss registers are used to hold the base address and offset.

3) In protected mode- uses all 24 address lines to access up to 16mb of physical memory.

4) It also provides 1gb of virtual memory using the descriptor table scheme.

• A 68-pin package is usally used for an 80286 microprocessor.

• 24-bit data bus allows the processor to access 16mb of physical memory when operating in protected mode.

• The even memory bank will be enabled when a0 is low and the odd bank will be enabled when bhe be low. To access aligned word, both a0 and bhe will be low.

• External buffers are used on both the address and data bus.

• Status signals s0 ,s1 and m/i0 are decoded by an external 82288 bus controller to produce the control bus read, write and interrupt-acknowledge signals.

• HOLD,HLDA,INTR,INTA,(NMI),READY, LOCK and RESET pins function same as in 8086.

• An external 82288 clock generator is used to produce clock signal and to synchronize RESET and READY signals.

• The processor extension request(PEREQ) pin will be asserted by a coprocessor to tell the 80286 to perform the data transfer to or from memory for it.

• PEACK is used to make coprocessor know that the data transfer has started.

• When 80286 executes a wait instruction, it will remain in wait until the BUSY signal is made high.

• ERROR- a coprocessor finds error.

Real Address Mode• When 80286 is in reset, it starts executing in real

mode.• here the physical memory is calculated by

directly adding an offset to the segment base address.

• In this case we can address 1mb of physical memory.

• Due to pipelining and other hardware inprovements it will execute faster then 8086 with the same frequency clock signal.

• In real mode the IVT of 80286 is located in the first 1kb of memory.

• Apart from interrupts similar to 8086 , it has additional interrupts:-

Interrupts:- asynchronous external events which affect the processor through the INTR or NMI input.

Exception:-generated by some error condition occurred during the execution. Ex-:software interrupts produced by the INT n instructions.

• Exceptions are further divided :- Faults:- are exception that detected and

signaled before the faulting instruction is executed. Ex:- segment not present.

Traps:-are exception that are reported after the instruction which caused the instruction executes. Ex:- divide by zero,

Protected Address Mode• First step to switch on to this mode is to

set the protection enable bit in the machine status word register.

• To change the bits of MSW we need to load the desired word in a register or memory location and execute the load machine status word(LMSW) instruction.

• Finally, execute an intersegment jump to the start of the main program in order to flush the instruction byte queue.

Implementation of segment –based virtual memory

• In this mode virtual address consists of 16-bit selector and a 16-bit offset.

• The mmu uses 14 bits of the selector to access a descriptor for the desired segment in a table of descriptors.

• The descriptor contains 24-bit physical base address.

• If the memory access meets the privilege test and the segment is present , the mmu will add the 16-bit offset from the logical address to the 24-bit base address for desired byte or word in the segment.

80286 New and Enhanced Instructions

Real‑ or protected‑mode instructions• INS‑Input string.• OUTS‑Output string.• PUSHA‑Push eight general‑purpose registers on stack.• POPA‑Pop eight general‑purpose registers from stack.• PUSH immediate‑Push immediate number on stack.• SHIFT/ROTATE destination, immediate‑Shift or rotate

des tination register or memory location specified number of bit positions.

• IMUL destination, immediate‑Signed multiply destination by immediate number.

• IMUL destination, multiplicand, immediate multiplier -Signed multiply, result in specified destination.

• ENTER‑Set up stack frame in procedure. Saves BP, points BP to TOS, and allocates stack space for local variables.

• LEAVE‑Undo ENTER actions before RET in procedure.

• BOUND‑Causes a type 5 execution if value in specified register is not within the specified range for an array.

• LMSW‑Load machine status word (LMSW) is used to switch the 80286 from real mode to protected mode.

Protected mode instructions• CTS‑Clear task‑switched flag in machine status word.• LGDT‑Load global descriptor table register from memory.• SGDT‑Store global descriptor table register contents in

memory.• LIDT‑Load interrupt descriptor table register from memory.• LLDT‑Load selector and associated descriptor into LDTR.• SLDT‑Store selector from LDTR in specified register or

memory.• LTR‑Load task register with selector and descriptor for TSS.• STR‑Store selector from task register in register or memory.• LMSW‑Load machine status register from register or memory.• SMSW‑Store machine status word in register or memory.

• LAR‑Load access rights byte of descriptor into register or memory.

• LSL‑Load segment limit from descriptor into register or memory.

• ARPL‑Adjust requested privilege level of selector (down only).

• VERR‑Determine if segment pointed to by selector is readable.

• VERW‑Determine if segment pointed to by selector is write able.