Some aspects of the DAQ for the Tile-HCAL Prototype

Volker Korbel, DESY, for the CALICE/Tile-HCAL groupMontpellier, France, 13-16 November 2003

Hadr. Calorimeter HCAL

•Analog version: scintillator tile read-out, small tile sizes, moderate granularity Si-PM or APD as sensors

•MiniCal:photodetectorsDAQ, Formats•Physics PrototypegranularityDAQ schemetrigger, ratesbeam time requiredpreamps, VFEtime schedule 2003/1004

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 2

Single looped fibre •strong fibre bending,•most stress on fibres,•probably ageing damages?

tiles, fibers, light yield

Centre/straight WLS-fibre Diagonal/bent WLS-fibre

No stress on fibre,fibre end reflector =tile reflector

L=7,85cmL=5cm

L=20cm

1.4 mm hole in centre •drilled and polished •For 5 cm straight WLS-fibre RO•cheep, for SiPM’s only

more stress on fibre,fibre end reflector =tile reflector

L=7.85cm

clear RO fibres:•l=1-3.5m to photo detector •light attenuation <18%

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 3

Photo-detectors

“Conventional” “Direct coupling”

Optical Connector +SiPM, APD

WLS&SIPM ---- 2 ways:

SiPM

Presented and discussed inBoris Dolgoshein’s andErika Garutti’s talks today.Si-PM’s (MEPHI/Pulsar):

1024 pixels, 1 mm2, on tile, gain ~ 106 at ~ 60V Ubias

need low noise fast preamplifiersAPD’s (Hamamatsu S8664-55spl)

3 x 3 mm2 photo-cathodes, gain ~200 at ~ 420V Ubias

need charge sensitive, low noise preamplifiersNeed special masks on photo-cathode for optical fibres

Light yield for MIP’s (used for calibration): 18-25 ph.e. on photo-cathode

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 4

MiniCal array, 1. prototype

Assembled with:•13 scintillator layers of 9 tiles in cassettes•with 117 scintillator tiles•117 Si-PM photo-detectors: 1 tile/Si-PM•36 photodetectors:

•APD’s or•3 MA-PMs,16 pix. each

•3 tiles/pixel

E-beam

E-beam

Aim of these studies:with cosmics, study of:•LY•uniformity of response•stability of MIP signals•different photodetectors•long term ageing•calibration with MIP’sLED monitoring:•stability•dynamic range measuremente-beam, study of:•energy resolution•constant term

X X X

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 5

MiniCal, visitors view

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 6

Status of DAQ (MiniCAL, I)

•Up to 200 ADC channels controlled via CAMAC

• CAMAC crate Power Supply current limits checked sufficient power for 22 ADC modules (2249A)

• synchronization of multiple ADCs at high rates (~1kHz) PC parallel port + special TTL-NIM adapter

Data Acquisition system for MiniCal:

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 7

Linear Collider I/O (LCIO)

“persistency” framework defining a data model for LC Studies

Generator

geometry

AnalysisRecon-structionSimulation

LCIO Persistency Framework

Java, C++, FortranGeant3, Geant4

Java, C++, Fortran Java, C++, Fortran

LCIO:- I/O Format agreed upon for LC related studies-Facilitates sharing of results-Originally developed for MC purposes (Mokka/Brahms) -Recent version v00-08 contains also data entities to store real data- Frank Gaede more info http://www-it.desy.de/~gaede

Data

(new)Detector

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 8

pad sizes, granularity, # of tiles

3, 6 and 12 cm

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 9

The Ppt DAQ concept

APD fibre masks orflat-band connector to Si-PM cassette RO printed circuit

~ 3m analogue RO

CALICE UK group, P. Dauncey

16 bit ADC‘s

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 10

The Ppt DAQ conceptEnergy measurement:16-bit ADC’s to cover large dynamic range between MIP’s (ch. 50) and 5 GeV on cell ( ~200 x larger)

Trigger:coincidence from beam- or cosmic-trigger coincidence, LED, min. biasLatency of overall trigger path < 180ns

This is from peak of shaping time in VFE chip for sample-and-hold

Jitter on trigger < 10nsTrigger sent after event, not beforeNo trigger from VFE level, some delay of analogue signals

Beam measurements:particle type, x-y, time, double hits in shaping time(early and late pile-up)

Beam counter, rate monitoring

slow controlsUbias, LV, temperatures, LED settings,...

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 11

DAQ rates, beam time request

Need high statistics for accurate simulation comparisonMultiple set-ups (energy, particle type, HCAL, angle, TC, etc) ~ 102

Need high statistics per set-up; accurate to 3 needs ~ 106 eventsNeed to take data in a reasonable time

For 108 events total, need around ~100 Hz average

>>> minimum 106 seconds is around two weeks continuous running time

Several months realistic beam time

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 12

The VFE-ROB-scheme, APD’s

Array ofsingle APD’s

n x 9 x 2

pulseshapers

Sample &

hold

Multiplexer

(analog)

Trigger/RO

clock

LED signals

PIN diode for LED

monitoring

HV,decoupled,common

value

charge sensitive preamps

HV, < 440 Von board

V/V~10-5

0,03 mA/ch

cosmic beam

Charge injection

DAC, pedestals

pedestals

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 13

The VFE-ROB-scheme, Si-PM’s

pulseshapers

Sample &

hold

Multiplexer

(analog)

Trigger/RO

clock

HV,decoupled

Receiver +PM

voltage fast preamps(gain variable ?

~10)

pedestals

HV on board,PC controlled

~ 60 VV/V~10-3

cosmic beam

Charge injectionDAC

Variable gain,3-4 steps

Signalsfrom Si-PM‘sin calo structure

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 14

ShS&H Mul

PrA

Orsay FLCHPY3

Dig. DATA

APD17(18)

ADCAD7677

16 bit1µsec/ch

HV

20 Sept.

VFE board development status, DubnaInput from Igor Tiapkin

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 15

FLC1

ADCLVDS1

LVDS2

DAC

HV

LVDS3

FLC2

FLC3

FLC4

Charge

injection

LEDtest

Dubna test board for CAMAC RO

Ready soonfor tests with CAMAC

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 16

R&D for Ppt, VFE prototype cards

VFE-Boards withLAL/Orsay•preamp chipsfor APD’s:

•LV supply•multiplexed ADC RO•HV-PS (500 V)•LED monitoring •multiplexing•VFE / CAMAC RO

2 options:

APD gain

>200:12 mV/7.2 fC

<100:12 mV/1.8 fC

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 17

1. Reading LAL/Orsay chip. Critical to the SH signal ±10nsec Multiplexer switching time ~100 nsec

2. ADC on board is ok.3. Data are in CAMAC.4. Now tests with 2 APD (and Si-PM’s) is going on.

Await soon:

1. Number of channels per board? 4 FLC chips - 72 channels

ADC AD7924 12bit, 4 ch, 1µsec.100-150 µsec readout time

• LED test?

need help from DESY for design (mechanics, exp. from H1)

• VME modules from UK?

need readout in spring 2004

Dubna, present status

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 18

VFE solution for Si-PMs

Have to inquire and take decision soon:•fast preamps, short gates, to reduce noise collection voltage amplifier ok?•fast preamp output to be gated by trigger (100-180 ns later)>>>needs: fast analogue delay lines or fast switch capacity memory downstream preamp ahead of shaping• how many channels/board (5000-8000 Si-PM’s ?)• Ubias, ~60V, remote set of +/0.1 V steps, 10 steps?

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 19

Dubna, next steps

Prot. test

Pilot boards production

Materials ?

HV testIf ok

LED calibr. Test?

NOW

Firstboard

Secondboard

2 months

1 month

?

End November,

HCAL main-meeting End of 2003

?

HV on board:

•APD ~400V generating on the board

(tuning for each channel probably not needed)

•SI-PM’s ~60V delivering to board, tuning for each channel

V. Korbel, DESY, CALICE Montpellier, France, 13-16 November 2003 20

the Ppt construction programPpt stack construction:

3 months tender and ordering3 months to build

Moving beam platform include in 6 month•More APD’s to order, have 58, need 150 (200), 2 month deliveryPress form for tile production: 4 monthsScintillator production >> tiles: 3months•Si-PMs

(~5000) 3 months production, 3 months acceptance tests2. batch (~3000) needed

•Acceptance tests with tiles with inserted Si-PM’s needs 3 months after production, 1. September finishedCassettes design to be fixed next 3 months, test neededAll equipped cassettes could be available in end October 2004•Decision on preamps and VFE logic for Si-PM’s and APD’s in 2003•Prototype VFE board from Dubna needed spring 2004• .>>>>>>>>all boards ready Sept.2004•CALICE-UK DAQ prototype ready 1. March 2004•March-August, System tests with cassettes, cosmic and DAQ at DESY, need increasing quantities of cassettes

Ppt e-beam test with ECAL at DESY in October 2004