Post on 16-Mar-2020
Chapter 8
Solving LargerSequential Problems
8. Solving Larger Sequential Problems
8.1 Shift Registers
8.2 Counters
8.3 Programmable Logic Devices (PLDs)
8.4 Design using ASM Diagrams
8.5 Hardware Design Languages
8.6 Data Control Devices
8.7 Analysis and Design Examples
* Devices and circuits that are used to control the flow of data
* Registers : devices to hold data temporarily and then move the data
* Timing and wave-shaping devices : to provide clocking and triggering synchronization
* Interfacing circuits are used to interconnect different subsystems
- decoders and encoders- multiplexers and demultiplexers- transceivers and buffers- D/A and A/D converters
8.1 Shift registers
★ Register* Consisted of a set of flip-flops, possibly with added combinational
gates, that perform data-processing tasks* Useful for storing, moving and manipulating data
★ Counter* Register that goes through a predetermined sequence of states upon
the application of clock pulses* Employed in circuits that sequence and control operations in a digital
system
★ Data registers
* Used to hold data temporarily and provide the correct timing for the movement of data
* Data bus : a highway where each lane represents a wire that is used to transmit a data bit
8.1 Shift registers
* Register capable of shifting its stored bits laterally in one or bothdirections
* Chain of flip-flops in cascade* 4-bit serial in-serial out shift register
★
8.1 Shift registers
* Parallel in-parallel out 4-bit data register that consists of only flip-flops without external gates
8.1 Shift registers
* Clock gating : the technique that the clock is turned on and off at the register clock inputs by the use of a logic gate
* Clock skew : the phenomenon that clock signals arrive at the flip-flops or registers at different times
8.1 Shift registers
* 4-bit register with parallel load : load & output feedback
8.1 Shift registers
* Serial transfer : Mode when information in the system is transferred or manipulated one bit at a time
* Parallel transfer, in which all the bits of the register are transferred at the same time
★ Serial addition
* 느리지만 하드웨어가 간단* 더해질 두 개의 이진수가 two shift registers 에 저장됨* Example of space-time trade-off* Parallel adder : combinational circuit* Serial adder : sequential circuit
8.1 Shift registers
* Example of serial transfer
* Conceptual diagram of serial and parallel data transfer
8.1 Shift registers
* Serial transfer
8.1 Shift registers
* Used to interface digital systems that are situated remotely from each other
8.1 Shift registers with parallel load
* Unidirectional shift register : a register capable of shifting in one direction only
* Bidirectional shift register : a register that can shift in both directions
8.1 Shift registers
8.1 Shift registers
8.1 Shift registers
8.1 Shift registers
★ Ripple counter
* Counter : a register that goes through a prescribed sequence of states upon the application of input pulses
* Binary counter following the binary number sequence* n-bit binary counter with n flip-flops* Ripple counter: the flip-flop output transition serves as a source for
triggering other flip-flops* Synchronous counter : clock inputs of all of the flip-flops receive the
common clock pulse, and the change of state isdetermined from the present state of the counter
* Flip-flop holding the least significant bit receives the incoming clock pulses
* Simple but unreliable and delay dependent
8.2 Counters
Ripple counter
8.2 Counters
* Up/down counting sequence of binary counter
8.2 Counters
* Design of binary counter: Binary counter with JK flip-flops
8.2 Counters
* K-maps for input equations of a binary counter
8.2 Counters
* Flip-flop input equations for the binary counter
* In an n-bit binary counter, the input equation for flip-flop Qi at any stage for i=1,2, …, n is
ENQQQKJENQQKJ
ENQKJENKJ
×××==
××==
×==
==
21033
1022
011
00
1
ENQQQQKJ iQiQi ×××××== -1210 L
8.2 Counters
* 4-bit synchronous binary counter
8.2 Counters
2) Counter with D flip-flops* Flip-flop input equations for the binary counter
* In an n-bit binary counter, the input equation for flip-flop Qi at any stage for i=1,2, …, n is
)(
)(
)(
21033
1022
011
00
ENQQQQDENQQQD
ENQQDENQD
Q
Q
Q
Q
×××Å=
××Å=
×Å=
Å=
)( 1210 ENQQQQQD iiQi ×××××Å= -L
8.2 Counters
* 4-bit synchronous binary counter with D flip-flops
8.2 Counters
★ Serial and parallel counters* Serial counter : counter having serial gating * Parallel counter : counter having parallel gating* Reduction in delay
★ Up-down binary counter using T-type flip-flops
* Input equations
* Carry outputs for the next stages
ENSQQQENSQQQTENSQQENSQQT
ENSQENSQTENT
A
A
A
A
××××+××××=
×××+×××=
××+××=
=
2102103
10102
001
0
countingdownwardforENSQQQQC
countingupwardforENSQQQQC
down
up
×××××=
×××××=
3210
3210
8.2 Counters
★ Binary counter with parallel load
8.2 Counters
* Function table
* BCD counter with load input
8.2 Counters
★ Ring counter
* A circulating shift register
* The first flip-flop's Q is preset to a 1, and all the rest of the flip-flops are cleared upon initialization
* The logic 1 is then made to circulate around the register
* The Q of the last flip-flop is fed back to the D input of the first flip-flop to form an endless ring or circle
* Output frequency
where fin : input clock frequency N : the number of flip-flops
Nff in
out =
8.2 Counters
* Duty cycle of the output waveform
* Inefficient and not self-starting
100N1cycleduty% ´=
8.2 Counters
* Timing diagram
8.2 Counters
★ Johnson counters
* A standard ring counter except that Qc of the last flip-flop is fed back to the input of the first flip-flop
* Twisted ring counter or switch tail counter* Output frequency
where fin : input clock frequencyN : the number of flip-flops
* Efficient and 50% duty cycle of the output waveform
N2f
f inout =
8.2 Counters
* Timing diagram of Johnson counter
8.2 Counters
★ Other counters
1) Divide-by-N counter (or modulo-N counter)* A counter that goes through a repeated sequence of N states
2) BCD counter
* Assuming T-type flip-flops for the counter* Simplified input equations
81
421818
214
812
1 1
QQYQQQQQT
QQTQQT
T
Q
Q
Q
Q
×=
××+×=
×=
×=
=
8.2 Counters
3) Arbitrary count sequence* Repeated sequence of six states
8.2 Counters
* Simplified input equations
* Logic & state diagrams
11==
====
CC
BB
AA
KBJKCJ
BKBJ
8.2 Counters
8.2 Counters
8.2 Counters
8.2 Counters
8.3 PLDs
8.3 PLDs
Structure of a PLA realization for an ASM.
8.3 PLDs
PLA realization with clocked D flip-flops for the ASM chart of Fig. 8.*
8.3 PLDs
Timing of an algorithmic state machine.
8.4 Design Using ASM Diagrams
8.4 Design Using ASM Diagrams
Two equivalent ASM blocks.
8.4 Design Using ASM Diagrams
8.4 Design Using ASM Diagrams
8.4 Design Using ASM Diagrams
ASM chart for a mod-8 binary counter
8.4 Design Using ASM Diagrams
ASM chart for a mod-8 binary up-down counter.
8.4 Design Using ASM Diagrams
ASM chart to recognize the sequence x1x2 = 01,01,11,00.
8.4 Design Using ASM Diagrams
Binary multiplication. (a) Pencil-and-paper approach. (b) Add-shift approach.
8.4 Design Using ASM Diagrams
Architecture for a binary multiplier.
8.4 Design Using ASM Diagrams
ASM chart for a binary multiplier.
8.4 Design Using ASM Diagrams
An ASM chart.Figure 8.*
8.4 Design Using ASM Diagrams
A minimum state locus assignment for the ASM chart of Fig. 8.*. (a) State-assignment map. (b) State locus.
8.4 Design Using ASM Diagrams
Karnaugh map for simplifying the function of Table 8.1b.+1Q
8.4 Design Using ASM Diagrams
Discrete-gate realization with clocked D flip-flops for the ASM chart of Fig. 8.*.
8.4 Design Using ASM Diagrams
Using variable-entered Karnaugh maps to obtain a discrete-gate realization with clocked D flip-flops for the ASM chart of Fig. 8.*.
8.4 Design Using ASM Diagrams
Using variable-entered Karnaugh maps to obtain a discrete-gate realization with clocked JK flip-flops for the ASM chart of Fig. 8.*.
8.4 Design Using ASM Diagrams
8.4 Design Using ASM Diagrams
8.5 Hardware Design Languages
★ Three-state control devices
* Three-state, or tristate logic devices are used to interface multiple devices onto a common bus
* Three possible output logic states
- logic 0 state- logic 1 state- hi-Z state (high
impedance state or disconnected state)
* Microcomputer system
8.6 Data Control Devices
* Three-state logic
8.6 Data Control Devices
★ Buffers* Devices that provide bus isolation and driving power in digital circuits* Inverting or noninverting* Buffers can be thought of as amplifiers
8.6 Data Control Devices
★ Schmitt trigger devices* Circuit that switches states at threshold or trigger points* Used as buffers to clean up distorted or slow-rising pulses
8.6 Data Control Devices
★ Transceivers* Unidirectional buffers : transceivers or receivers* Bidirectional device that can transmit or receive data in either
direction but not at the same time
8.6 Data Control Devices
* TTL and CMOS interface devices
8.6 Data Control Devices
★ Data converters* Used to change data from one format to another
* BCD to decimal, analog to digital, parallel to serial
★ Decoders and encoders* Used to convert data from one format to another* Encoding: the process of converting from a primary coding system to
a secondary system* Decoding : the process of converting from a secondary coding system to a primary system
8.6 Data Control Devices
★ Digital-to-analog converters
* Binary-weighted ladder DAC* Resolution: a measure of how fine the output voltage steps or
increments will be
where n : the number of input bits[Ex1] 8-bit DAC : 0.39%[Ex2] 4-bit DAC : 6.25%
%10021resolution n ´=
8.6 Data Control Devices
* Accuracy : a measure of the difference between the expected voltage output and the actual voltage output
* Conversion time- the time required for a DAC to produce an output voltage- the time required to produce a full-scale output voltage when
the input is changed from all zeros to all ones- settling time
%100v
vvaccuracy
exp
actexp ´-
=
8.6 Data Control Devices
* Offset voltage : the DAC output voltage when the binary inputs are all zeros
8.6 Data Control Devices
★ Analog-to digital converters* The basic op-amp comparator which functions as a switch can be
used for ADC* When the input voltage is equal to or greater than the reference
voltage, the comparator will produce an output
8.6 Data Control Devices
8.6 Data Control Devices
★ Universal asynchronous receiver transmitter (UART)
1) A type of serial-to-parallel or parallel-to-serial data converter
2) Serial data format
* Control bits : to separate each parallel data word length in the serial format as well as to define the word length and type of parity being used
* Start bit : beginning of data
8.6 Data Control Devices
8.6 Data Control Devices
★ Design Example :Twelve-hour clock(1)
8.7 Analysis and Design Examples
Design Example : Twelve-hour clock(2)
8.7 Analysis and Design Examples
★ Analysis examples
1) 그림 1의 디지털 회로에 대하여 아래에 답하시오.
(1) input equations 및 output equations를 구하시오.(2) state table을 구하시오.(3) state diagram을 구하시오.(4) 다음 그림 2와과 같은 clock 과 입력(x)에 대한 3개의 출력 파형(F1, F2, z)을 그리시오.
8.7 Analysis and Design Examples
8.7 Analysis and Design Examples
해) * Input equations
* State table 212
211
FFxDxFFD
+=
=
Presentstate
Next state
0 1
F2 F1 F2 F1 z F2 F1 z
0 0 0 1 0 0 0 0
0 1 0 1 0 1 1 0
1 0 0 1 0 0 0 1
1 1 0 1 0 0 0 1
8.7 Analysis and Design Examples
* State diagram
* Timing diagram
A
D C
B
x/z
yx /z
x ' /z 'x /z '
x ' /z '
x ' /z '
x /z '
F2
x
CLO CK
BF1
A B D B D A B
z
8.7 Analysis and Design Examples