Post on 12-Sep-2021
Research frontiers inResearch frontiers in DFT and BISTStephen SunterEngineering Director, Mixed-signal DFT
Silicon Test SolutionsSilicon Test Solutions
June 2011
stephen_sunter a t mentor . com
Introduction
Evolution of DFT techniques for random logic and memory— Scan-path test access: adoption started ~1986; widely used nowScan path test access: adoption started 1986; widely used now— Boundary scan: adoption started ~1993; widely used— Memory BIST: adoption started ~1996; widely used
– At-speed programmable memory write-through— Scan compression: adoption started ~2001; increasing usage
– 10X~100X compression at-speed controlled power— Logic BIST: adoption started ~2003; increasing usage
At speed async multi frequency controlled power– At-speed async. multi-frequency controlled power
Evolution of DFT techniques for analog/mixed-signal/RF— Loopback, and analog bus – adoption started ~1975; widely used— BIST – ad hoc; minimal adoption
System-on-chip test effort and costs: 70% mixed-signal— As reported by Infineon, Qualcomm (for cellphone ICs)
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As reported by Infineon, Qualcomm (for cellphone ICs)— Need systematic DFT!
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F. Poehl et al., “Production test challenges for highly integrated mobile phone SoCs - A case study”, Eur. Test Symp. 2010
K. Arabi , “Mixed-Signal Test Impact to SoC Commercialization” VLSI Test Symp., 2010
Outline
3D test problems, and DFT standards— Some details for 1149.4 and P1687Some details for 1149.4 and P1687
Review of industry techniques for mixed-signal DFT/BIST — PLL
SerDes— SerDes— DDR I/Os— Other I/Os— ADC/DACADC/DAC— Analog— RF
Concl sions Conclusions
EDN Jan. 2010 EDN Nov. 2010
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3D test problemsp
Require known good die (KGD)— Final-test fault coverage at wafer-sortFinal test fault coverage at wafer sort— Inductance+resistance of probe access
Reduced access after packagingFewer pins per IC than single die packages— Fewer pins per IC than single die packages
— No visual access to each die for diagnosis
More chip I/Os (TSVs)— Reduced area per I/O for test circuitry— Higher probability of faulty connections to other ICs
Higher defectivity at package-level Higher defectivity at package level— Many ICs per package (with
lower pre-package fault coverage)— TSV yield needs improvement
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y p
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DFT standards for 3D applications pp
Must test packaged IC via only 1149.x interface
IEEE t d d f t ti hi I/O d ti IEEE standards for testing chip I/Os and connections— 1149.1 (JTAG boundary scan) – 4 or 5 pins
– Detect shorts/opens between connected I/Os, and control BIST1149 4 (analog boundary scan) additional 2 or 4 pins *— 1149.4 (analog boundary scan) – additional 2 or 4 pins *
– Apply currents and measure voltages at I/Os, and in core— 1149.6 (ACJTAG) – boundary scan for differential or AC interconnect
– Apply TCK-rate square waves, and detect edge pulsespp y q , g p— 1149.7 – reduced-pin 1149.1 test access ports
– Also allows multiple TAPs to share same package pins
IEEE standards for testing chip core IEEE standards for testing chip core— 1500 (embedded core test access) – scan wrappers & description— P1687 (IJTAG: Instrument JTAG) – access to test-instruments *— P1838 (test access to 3D stacked ICs)
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( )
Lots for digital; very little for analog5
1149.4 standard mixed-signal (analog) test busg ( g)
Overview presented to CMC May 16 by Heiko Ehrenberg
IEEE i d i 2000 b t d t d i 2011 t i l d ABSDL IEEE issued in 2000, but updated in 2011 to include ABSDL— Analog boundary scan description language— Facilitates automated test generation
Limitations, .4 solutions, more limitations— Maximum number of access-transistor diffusions per wire
– DC leakage current before 100µA max reached <10 nodes is OK– AC coupling for HF signals, even in function mode good T switches– Capacitance limits bandwidth analog buffers
— Maximum length of interconnect– Capacitance limits bandwidth; inductance limits SNRCapacitance limits bandwidth; inductance limits SNR– Antenna effect/plasma-induced damage requires diffusions, capacitance
— Solution: Multiple busses + analog multiplexer to AT1/AT2– Limitation: Wiring congestion if >200 nodes
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– Limitation: Still must traverse the whole IC– Limitation: Bus+switches+buffers limit bandwidth, SNR, linearity, offset
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P1687 standard for on-chip instrument accessp
Proposed IEEE standard— Being developed by >20 major companiesBeing developed by >20 major companies— Standard digital access to on-chip test capabilities (instruments)
Programmable length scan path accessMinimizes access time to any instrument— Minimizes access time to any instrument
Language that describes how to access any instrument— Allows automated retargeting of test patterns— Simplifies creation of test patterns— Facilitates creating tests that involve instruments on multiple ICs
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7Source: http://grouper.ieee.org/groups/1687/documentation.html
Analog/mixed-signal DFTg/ g
All DFT standards focus on digital— Except 1149.4, which hardly anyone usesExcept 1149.4, which hardly anyone uses— AMS test is growing to >70% of total test
Overview of industry techniques for mixed signal DFTTest Time Distribution
Overview of industry techniques for mixed-signal DFT— Focus on relevance to 3D— PLL— SerDes fSerDes— DDR I/Os— General I/Os— ADC/DAC
Key specifications DFT techniquesBIST techniquesMost common techniqueADC/DAC
— Analog— RF
Most common techniqueEmerging problems
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8Pie chart source: F. Poehl et al., “Production test challenges for highly integrated mobile phone SoCs - A case study”, Eur. Test Symp. 2010
PLL
Key specificationsJitter <5 ps rms Duty cycle = 50% ±2%Jitter <5 ps rms Duty cycle 50% ±2%Lock time <10 µs Lock range = 100 MHz ~ 2 GHz
DFT techniquesConnect divided down clock to I/O pin to measure frequency jitter— Connect divided-down clock to I/O pin to measure frequency, jitter
— Connect analog bus to VCO control voltage to measure VCO range
BIST techniques— Delay-line from ref. clock to sampling latch to measure jitter— Undersample with offset frequency to measure jitter, duty cycle— Count ref. clock cycles from forced loss-of-lock until lock regained
Most common technique— No dedicated PLL test: simply wait lock time, then test core logic
Emerging problems
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Emerging problems— All-digital PLLs – need prod’n test until proven in volume— PLL affects product-level specifications
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Mentor’s Tessent PLLTest™
Measures with calibrated 0 5ps~0 5ms resolution0.5ps~0.5ms resolution, in 10ms
Jitter— Input, output— HF, LF
Phase errorRefClock
PLLout Phase error
Frequency, duty cycle
Lock time, range
PLLout
PLLchange Lock time, range
Proven on customer silicon to <1 ps rms
Sampling clock from another on-chip PLL, or off-chip PLL
LockDetect
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Sampling clock from another on chip PLL, or off chip PLL
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US patent: 7158899Sunter & Roy, “Noise-insensitive digital BIST for any PLL or DLL”, J. of Elect. Testing: Theory and App., Oct. 2008R. Kinger et al., “Experiences with parametric BIST for production testing PLLs with picosecond precision”,
Int’l Test Conf., Nov. 2010
SerDes I/O/
Key specifications (>4Gb/s)Random jitter <2 ps rms Duty cycle = 50% ±1%Random jitter <2 ps rms Duty cycle 50% ±1%Amplitude >500 mV ISI <20 ps p-p
DFT techniquesIn receiver add 2nd comparator with adjust V to monitor signals— In receiver, add 2nd comparator with adjust. VREF to monitor signals
— Add multiple on-chip loopback paths (serial, parallel, pre/post filter)
BIST techniques— PRBS generate+compare, for loopback bit error rate test (BERT)— Programmable phase-interpolator to sample anywhere in signal eye— Offset ref. frequency for receiver to undersample input signal
Most common technique— Loopback PRBS, and detect no bit errors in <500 ms
Emerging problems
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Emerging problems— ISI from inter-chip wiring dominates – must test equalization— ATE too expensive, impractical >5 Gb/s
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Mentor’s Tessent SerdesTest™
Measures with calibrated 0 1ps~0 1ms resolution0.1ps~0.1ms resolution, in 10ms
Waveform— Rise time, slew rate
Jitter— RJRMS TJRMS (with LF rejection)RJRMS, TJRMS (with LF rejection)— DJP-P (DCD, ISI)
Jitter toleranceE li ti— Equalization
— Sampling instant (mean, variation)— BER
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Proven on customer silicon >10 Gb/s, >50 lanes, <1 ps rms
12US patents: 7158899, 7453255Sunter & Roy, “Structural tests for jitter tolerance in SerDes receivers”, Int’l Test Conf., 2005
DDR I/O/
Key specifications (>800 Mb/s per pin)Crosstalk <50 ps Duty cycle = 50% ±1%Crosstalk <50 ps Duty cycle 50% ±1%Slew rate 1V/ns Skew <20 ps across 8 pins
DFT techniquesSelectable DLL outputs to sample multiple time points in DQ signal— Selectable DLL outputs to sample multiple time points in DQ signal
BIST techniques— Pseudo-random word or 1010 generate+compare, for loopback— Delay line in clock for DQ pin receivers— Offset ref. frequency for receiver or boundary scan to undersample
Most common technique Most common technique— Functional testing by ATE
Emerging problemsATE t i 1 Gb/ (h d d f I/O )
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— ATE too expensive >1 Gb/s (hundreds of I/Os)— DDR used widely for chip-to-chip in 3D; at rapidly increasing speeds
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General I/O/
Key specifications (<100 Mb/s per pin)IIL, IIH <10 µA VOL/IOL, VOH/IOL <50 ΩIIL, IIH <10 µA VOL/IOL, VOH/IOL <50 ΩSlew rate limiting Setup/hold time
DFT techniquesBoundary scan— Boundary scan
— All I/Os bidirectional
BIST techniques— Programmable pull-up/down; test that it overdrives leakage— Adjustable boundary scan updatecapture timing
Most common technique Most common technique— Bidirectional I/O + boundary scan
Emerging problemsT ti I/O ti i i l d b d
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— Testing I/O connections on increasingly dense boards— Boundary scan may be too intrusive when 1000s of TSVs— Testing TSV quality
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Mentor’s IOTest™ (in development)( p )
Measures delays— I/O wrap, rising, fallingI/O wrap, rising, falling— SSN, rise/fall mismatch,
pin-to-pin mismatch
Unlimited time resolution analysis (ns~ps) Unlimited time-resolution analysis (ns~ps)— Uses async clock from PLL for capture— No calibration or sensitivity to PVT— No changes to boundary scan cellsNo changes to boundary scan cells— Suitable for all I/Os, including DDR
Shifts out measured values, or pass/fail vs. per-pin limitsM b f i i lt l— Measure any number of pins simultaneously
RTL-synthesized, purely digital
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US patents: 7453255, others pendingSunter & Tilmann, “BIST of I/O circuit parameters via standard boundary scan”, Int’l Test Conf., 2010Sunter & Roy, “Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan”,
Int’l Test Conf., 2011
ADC/DACD/A A/D
/
Key specificationsDNL,INL <1 LSB Aperture jitter <1 LSB equiv. (<2 ps rms)DNL,INL <1 LSB Aperture jitter <1 LSB equiv. (<2 ps rms)SFDR >6 dB/bit SNR >5 dB/bit
DFT techniquesScan access to digital; analog bus access to analog— Scan access to digital; analog bus access to analog
— Loopback, with offset voltage injection 1
BIST techniques— On-chip linear ramp generation (~10 bits linearity)— Use DSP to perform FFT
Most common technique Most common technique— Functional testing by ATE
Emerging problemsE b dd d fl h & l RAM 1 i t t t d lti it t t
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— Embedded flash & large RAM >1 minute test – need multi-site test— Too many converters for ATE (10~100), especially if multi-site
161 L.Jin, et al., “Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal”, IEEE Trans. on Instr. And Meas., June 2005
Random analogg
Key specificationsSlew rate Overshoot PSRRSlew rate Overshoot PSRRGain DC voltage etc.
DFT techniquesScan access to digital; analog bus (or multiplexer) access to analog— Scan access to digital; analog bus (or multiplexer) access to analog
— Ad hoc
BIST techniques— Ad hoc
Most common technique— Functional testing by ATE via analog bus F. Poehl et al., “Production test challenges for highly integrated
bil h S C A t d ” E T t S 2010Functional testing by ATE, via analog bus
Emerging problems— Too many functions for ad hoc approach; unpredictable TTM
T littl f l ti t d d
mobile phone SoCs - A case study”, Eur. Test Symp. 2010
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— Too little reuse of solutions; no standards— Insufficient engineers with analog test skills
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Mentor’s Analog DFT/BIST (in development)g / ( p )
Three principles— Unlimited voltage resolution: PWM, sigma-delta, oversamplingUnlimited voltage resolution: PWM, sigma delta, oversampling — Unlimited time resolution: undersampling periodic signals— Unlimited number of nodes: 2 shift registers, 1687-like addressing
Stimulus CUT Response
Four building blocks— Shared digital stimulus generation + stimulus shift reg.
Stimulusgenerator Shift register CUTD/A A/D Shift register
panalyser
D/A A/DCUT
– Clock-like waveform, PWM, sigma-delta, …— Simple D/A conversion
– No need to test it, eg. RCSimple A/D conversion— Simple A/D conversion
– No need to test it, eg. sampling comparator— Response shift reg. + shared digital response analysis
– Accumulator, timing analyser, DSP, …
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, g y , ,
Serial digital version of 1149.4 18
Sunter & Roy, “A mixed-signal test bus and analog BIST with ‘unlimited’ time and voltage resolution”, Eur. Test Symp., 2011
RF analogg
Key specificationsThird-order intercept Output powerThird order intercept Output powerBandwidth, frequency Noise
DFT techniquesAnalog bus to monitor V V— Analog bus to monitor VBIAS
— Analog bus to monitor power detector VDC— Down-mixer
VDC
BIST techniques— Loopback
Most common technique Most common technique— Functional testing by ATE
Emerging problemsC t lk b t di f hi
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— Crosstalk between radios of a chip— Crosstalk during multi-site test
19Zhang et al., “Low Cost RF Receiver Parameter Measurement with On-chip Amplitude Detectors”, VLSI Test Symp., 2008
Conclusions
3D packaging introduces test problems— KGD, less access, more I/Os, interconnect yieldKGD, less access, more I/Os, interconnect yield
DFT standards mostly applicable to digital test— 1149.1, 1149.6, 1149.7, 1500, P1687
1149 4 has many limitations due to its analog nature— 1149.4 has many limitations due to its analog nature
Varying amounts of DFT/BIST adoption in industry— PLL— SerDes— DDR I/Os— General I/Os
ADC/DAC
Synopsys2%
BIST2010 BIST market shareOther
— ADC/DAC— Analog— RF
Mentor98%Mentor
98%
Source: EDAC April 2011
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Mentor is the only company providing general DFT/BIST solutions
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Source: EDAC April 2011