The BIST History of FPGAs The BISTory of FPGAsagrawvd/D&TSEMINAR_SPR06/SLIDES... · The BIST...

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The BIST History of The BIST History of FPGAsFPGAs

Chuck StroudChuck StroudElectrical and Computer EngineeringElectrical and Computer Engineering

Auburn UniversityAuburn University

The The BISToryBISTory of of FPGAsFPGAs

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Outline of PresentationOutline of Presentation��BackgroundBackground

��Overview of Overview of FPGAsFPGAs & FPGA Testing& FPGA Testing

��My Experience in My Experience in FPGAsFPGAs

��BIST Approaches for BIST Approaches for FPGAsFPGAs��Logic BIST ApproachesLogic BIST Approaches

��CAD Tool Features vs. TestabilityCAD Tool Features vs. Testability

��Routing BIST ApproachesRouting BIST Approaches

��Other Cores & ResourcesOther Cores & Resources

��Embedded ProcessorEmbedded Processor--Based BISTBased BIST

��SummarySummary

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FPGA CharacteristicsFPGA Characteristics��Configuration memoryConfiguration memory

��32K 32K -- 50M bits50M bits

��Array of Programmable Logic Blocks (Array of Programmable Logic Blocks (PLBsPLBs))��100 100 -- 22,270 22,270 PLBsPLBs per FPGAper FPGA

��11--8 48 4--input input LUTsLUTs and 1and 1--8 flip8 flip--flops per PLBflops per PLB

��Programmable interconnect networkProgrammable interconnect network��Wire segmentsWire segments

��50 50 -- 400 per PLB400 per PLB

��Programmable switchesProgrammable switches��80 80 -- 2,400 per PLB2,400 per PLB

��Programmable I/O cellsProgrammable I/O cells��BiBi--direction buffer with flipdirection buffer with flip--flops/latchesflops/latches

��50 50 -- 750 per FPGA750 per FPGA

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Important Trends in FPGAsImportant Trends in FPGAs��Dynamic partial reconfigurationDynamic partial reconfiguration�� Incorporating specialized coresIncorporating specialized cores

��RAMs RAMs -- singlesingle--port, dualport, dual--port, FIFO, ECCport, FIFO, ECC��128 128 -- 18K bits per RAM18K bits per RAM��4 4 -- 550 per FPGA550 per FPGA

��DSPsDSPs including multipliers, accumulators, etc.including multipliers, accumulators, etc.��30 30 -- 510 per FPGA510 per FPGA

��Embedded processor coresEmbedded processor cores��Up to 2 hard cores per FPGAUp to 2 hard cores per FPGA��Also support soft processor cores synthesized in FPGAAlso support soft processor cores synthesized in FPGA

�� Internal access to configuration memoryInternal access to configuration memory��Write and read access by embedded processor coreWrite and read access by embedded processor core

��FPGAs becoming more like FPGAs becoming more like SoCsSoCs��ASICs & ASICs & SoCsSoCs now incorporate FPGA coresnow incorporate FPGA cores

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FPGA Testing ChallengesFPGA Testing Challenges��ProgrammabilityProgrammability

��Must test all modes of operationMust test all modes of operation

��Architectures designed for applicationsArchitectures designed for applications��Testing issues/problems left to product/test engineersTesting issues/problems left to product/test engineers

��CAD tools designed for highCAD tools designed for high--level synthesislevel synthesis��Do not support control of proper test conditionsDo not support control of proper test conditions

��Constantly growing sizesConstantly growing sizes��Reconfiguration dominates test timeReconfiguration dominates test time

��Constantly changing architecturesConstantly changing architectures��Architectural features/limitations directly affect Architectural features/limitations directly affect

testability and test developmenttestability and test development

�� Incorporation of many new/different coresIncorporation of many new/different cores

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FPGA TestingFPGA Testing��Typically partitioned for logic and routingTypically partitioned for logic and routing

��But both resources needed to test each otherBut both resources needed to test each other

��External testingExternal testing��Good for manufacture testing onlyGood for manufacture testing only

��Tests applied via I/O pinsTests applied via I/O pins��Package dependent and limited by I/O pinsPackage dependent and limited by I/O pins

��Boundary Scan (only with INTEST)Boundary Scan (only with INTEST)��Extremely long test timeExtremely long test time

�� Internal Testing (BIST)Internal Testing (BIST)��Good for manufacturing & systemGood for manufacturing & system--level testlevel test

��Good for embedded FPGA coresGood for embedded FPGA cores

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FPGA TestingFPGA Testing��Application independent testingApplication independent testing

��Test all resources in FPGATest all resources in FPGA��Good for manufacturing testingGood for manufacturing testing

��Requires Requires manymany test configurationstest configurations��Long test time Long test time -- downloads dominate test timedownloads dominate test time

��No area/performance penalty in systemNo area/performance penalty in system

��Application specific testingApplication specific testing��Test only resources used by system functionTest only resources used by system function��Requires fewer configurationsRequires fewer configurations

��But requires new tests for new applicationsBut requires new tests for new applications��Good for systemGood for system--level testing onlylevel testing only

��Area/performance penalty for test circuitryArea/performance penalty for test circuitry

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SystemSystem--Level FPGA TestingLevel FPGA Testing

��SystemSystem--level test of FPGAlevel test of FPGA--based designsbased designs��Diagnostic software for test in system modeDiagnostic software for test in system mode

��Many months of diagnostic code developmentMany months of diagnostic code development

��Good diagnostic resolution difficult to achieveGood diagnostic resolution difficult to achieve

��DFT/BIST in FPGA (for systemDFT/BIST in FPGA (for system--level test)level test)��Area penalty typically 10Area penalty typically 10--30%30%��Performance penalty typically 2Performance penalty typically 2--3 gate delays3 gate delays��Less logic for system functionLess logic for system function��Longer design timeLonger design time

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BIST for BIST for FPGAsFPGAs��Basic idea:Basic idea: reprogram FPGA to test itselfreprogram FPGA to test itself

��BIST logic disappears after testBIST logic disappears after test��No area overhead or performance penaltiesNo area overhead or performance penalties

��Applicable to all levels of testingApplicable to all levels of testing��Application independent testingApplication independent testing��A generic test for a generic componentA generic test for a generic component��Good diagnostic resolutionGood diagnostic resolution

��To faulty PLB or wire segment/switch within FPGATo faulty PLB or wire segment/switch within FPGA��No diagnostic code development or DFT designNo diagnostic code development or DFT design

��Cost:Cost:��Memory to store BIST configurationsMemory to store BIST configurations

��Goal:Goal: minimize number of configurationsminimize number of configurations

��Download time to execute BIST configurationsDownload time to execute BIST configurations��Goal:Goal: minimize downloadsminimize downloads

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My BIST & FPGA BackgroundMy BIST & FPGA Background

��Bell Labs (1977Bell Labs (1977--93)93)��Telecommunications systemsTelecommunications systems��I designedI designed

��21 production VLSI devices21 production VLSI devices��Prototype boards for over half of thesePrototype boards for over half of these

��3 production printed circuit boards3 production printed circuit boards

��1981 1981 -- began work on BISTbegan work on BIST��Most VLSI devices included BISTMost VLSI devices included BIST

��1984 1984 -- began work on began work on FPGAsFPGAs��1985 1985 -- began work on synthesis toolsbegan work on synthesis tools��1987 1987 -- first mixedfirst mixed--signal BISTsignal BIST

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Initial Work on Initial Work on FPGAsFPGAs��Bread board Bread board ASICsASICs in design methodologyin design methodology

��We used TTL and fusedWe used TTL and fused--based based PALsPALs in early 1980sin early 1980s�� I designed RAMI designed RAM--based programmable device in 1984based programmable device in 1984

��Soft Programmable Logic Array Technology (SPLAT)Soft Programmable Logic Array Technology (SPLAT)��My original idea of BIST for My original idea of BIST for FPGAsFPGAs::

�� program for program for ““easiereasier”” testingtesting

��Needed synthesis tool to program SPLATNeeded synthesis tool to program SPLAT��Began development of CONES in 1985Began development of CONES in 1985��Synthesized behavioral models written in C toSynthesized behavioral models written in C to

��Standard cell based Standard cell based ASICsASICs��PLDPLD--based bread boards and PCBsbased bread boards and PCBs

�� Used 22V10s and 16V8s and considered use of Xilinx LCAUsed 22V10s and 16V8s and considered use of Xilinx LCA�� Refined idea of BIST for Refined idea of BIST for FPGAsFPGAs::

�� program for BIST and diagnosis program for BIST and diagnosis –– can route around faultscan route around faults

��CONES became a design methodologyCONES became a design methodology��Widely used at Bell Labs until early 1990s (then VHDL)Widely used at Bell Labs until early 1990s (then VHDL)

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BIST for BIST for FPGAsFPGAs�� Started actual work on BIST for Started actual work on BIST for FPGAsFPGAs in 1993in 1993

�� No one had done it (No one had done it (nothing in literaturenothing in literature))�� Good area for academic R&D starting at Univ. of Good area for academic R&D starting at Univ. of KyKy

�� OffOff--line BIST and diagnosis of line BIST and diagnosis of FPGAsFPGAs�� Funded by Bell Labs, NSF & UK CRMS (1993Funded by Bell Labs, NSF & UK CRMS (1993--1998)1998)�� ORCA 2C and 2CA seriesORCA 2C and 2CA series

�� Also some preliminary BIST work for ORCA 3C and 4 seriesAlso some preliminary BIST work for ORCA 3C and 4 series�� MironMiron AbramoviciAbramovici at Bell Labs joined me in 1994at Bell Labs joined me in 1994

�� Expertise in ATPG, DFT, and diagnosis of Expertise in ATPG, DFT, and diagnosis of ASICsASICs

�� OnOn--line BIST, diagnosis, and faultline BIST, diagnosis, and fault--tolerancetolerance�� Funded by DARPA and Funded by DARPA and LucentLucent→→AgereAgere (1997 (1997 -- 2001)2001)�� Used ORCA 2C/2CA due to dynamic partial reconfigurationUsed ORCA 2C/2CA due to dynamic partial reconfiguration

�� Considered Xilinx 6800 seriesConsidered Xilinx 6800 series�� John John EmmertEmmert joined myself and joined myself and MironMiron AbramoviciAbramovici in 1999in 1999

�� Expertise in faultExpertise in fault--tolerant approaches in tolerant approaches in FPGAsFPGAs

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More BIST for More BIST for FPGAsFPGAs��Manufacturing test development and BISTManufacturing test development and BIST

��Funded by Cypress & UK CRMS (1997Funded by Cypress & UK CRMS (1997––2000)2000)��Cypress Delta 39K seriesCypress Delta 39K series

��Some initial work on 37K series Some initial work on 37K series CPLDsCPLDs

�� Included (besides logic and routing)Included (besides logic and routing)��BIST for embedded BIST for embedded RAMsRAMs and and FIFOsFIFOs��Embedded logic analyzerEmbedded logic analyzer

�� Similar to Xilinx Similar to Xilinx ChipScopeChipScope

��Embedded processorEmbedded processor--based BISTbased BIST��Funded by NSA & US Army SMDC (2003Funded by NSA & US Army SMDC (2003--2006)2006)��Atmel AT94K series FPSLICAtmel AT94K series FPSLIC

��Also applicable to AT40K series FPGAAlso applicable to AT40K series FPGA

�� Included (besides logic and routing)Included (besides logic and routing)��BIST for embedded BIST for embedded RAMsRAMs and I/O buffersand I/O buffers��Guard bands and failGuard bands and fail--silent operationsilent operation

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BIST for Xilinx BIST for Xilinx FPGAsFPGAs�� 4000 & Spartan series4000 & Spartan series

�� Funded by NSA & NC Space Consortium (2001Funded by NSA & NC Space Consortium (2001--2003)2003)�� 4000E, 4000XL/XLA, Spartan4000E, 4000XL/XLA, Spartan�� BIST for logic and routing resourcesBIST for logic and routing resources

�� VirtexVirtex--I, I, VirtexVirtex--II Pro, SpartanII Pro, Spartan--II, SpartanII, Spartan--33�� Funded by NSA (2004Funded by NSA (2004--2005)2005)�� Preliminary work in Preliminary work in

�� BIST and diagnosisBIST and diagnosis�� Logic, routing, I/O buffers, embedded Logic, routing, I/O buffers, embedded RAMsRAMs, multipliers, multipliers�� Dynamic partial reconfigurationDynamic partial reconfiguration�� Partial configuration memory read backPartial configuration memory read back

�� Guard bands and failGuard bands and fail--silent operationsilent operation�� Embedded processorEmbedded processor--based BIST for based BIST for VirtexVirtex--II ProII Pro

�� VirtexVirtex--44�� Funded by NSA (2005Funded by NSA (2005--2006)2006)�� BIST for logic, routing, I/O buffers, BIST for logic, routing, I/O buffers, RAMsRAMs, , DSPsDSPs

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Our FPGA BIST ConfigurationsOur FPGA BIST Configurations

15215212812812124000E/Spartan4000E/Spartan23023020620612124000XL/XLA4000XL/XLA3073072832831212VirtexVirtex--I/SpartanI/Spartan--IIII

6464565644AT94K/40KAT94K/40KAtmelAtmel459459419419202039K39KCypressCypress

XilinxXilinx

ORCAORCA

FPGAFPGA

??

76766666

TotalTotal

??1515VirtexVirtex--44

484814142CA2CA27 (48)27 (48)992C2C

RoutingRoutingLogicLogic

Notes: Logic BIST configurations are applied 2 timesConfigurations for embedded cores not included

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Other Work in FPGA TestingOther Work in FPGA Testing��Lombardi & HuangLombardi & Huang

��External testing of logic and routingExternal testing of logic and routing��Xilinx 4000 and Xilinx 4000 and AlteraAltera

��RenovellRenovell and and ZorianZorian (with others)(with others)��Test configurations for logic and routingTest configurations for logic and routing

��Xilinx 4000 and ORCAXilinx 4000 and ORCA

��Harris and Harris and TessierTessier��BIST configurations for routingBIST configurations for routing

��Xilinx 4000 and Xilinx 4000 and VirtexVirtex

��Sun and ChanSun and Chan��ParityParity--based BIST for routingbased BIST for routing

��Xilinx 4000Xilinx 4000

��TahooriTahoori��Application dependent testing of logic and routingApplication dependent testing of logic and routing

��Xilinx Xilinx VirtexVirtex

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First Logic BIST ApproachFirst Logic BIST Approach

O

TPGTPG

TPG BUTBUT

BUTBUT

BUTBUT

BUTBUT

LUTLUT FFFF

ORAORA

LUTLUT FFFF

ORAORA

......

...

...

BISTBIST startstart

pass/fail

pass/fail

.. .C+1

C+1m

m

O

O

O

��Schematic entry difficultSchematic entry difficult��Manual placement needed to test all Manual placement needed to test all PLBsPLBs

��Routing difficult with larger Routing difficult with larger NNxxNN arraysarrays��Routing complexity = Routing complexity = OO((NN22))

��Global routing resources heavily usedGlobal routing resources heavily used

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Second Logic BIST (Second Logic BIST (Iterative Logic ArrayIterative Logic Array) )

BUTs

BUTs

BUTs

BUTs

Helpers

Helpers

Helpers

Helpers

TP

G(s

) OR

AO

RA

BUTs

BUTs

BUTs

BUTsHelpers

Helpers

Helpers

Helpers

TP

G(s

)

OR

AO

RA

BU

Ts

BU

Ts

Hel

persunused

PLBs

Hel

pers

TPG

ORA

BUTBUT

helperhelper

ILA cellILA cell

BUTBUT

helperhelper

ILAILA cellcell

BUTBUT

helperhelper

ILA cellILA cell

ORAORA

from other ILAfrom other ILA

global routingglobal routing

locallocalroutingrouting

locallocalroutingrouting

TPGTPG

��Advantages:Advantages:��Linear routing complexityLinear routing complexity��Easily scaleableEasily scaleable��Algorithmic PLB placement & routing with NCLAlgorithmic PLB placement & routing with NCL

��Disadvantages:Disadvantages:��3 test sessions3 test sessions��Difficult to propagate test patterns through Difficult to propagate test patterns through BUTsBUTs

��Particularly for sequential logic functionsParticularly for sequential logic functions

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Third Logic BIST (Third Logic BIST (HybridHybrid))TPGTPGBUTBUTORAORABUTBUTORAORABUTBUTORAORABUTBUTTPGTPG

BUTBUTORAORABUTBUTORAORABUTBUTORAORABUTBUT

� Two test sessions� Row or column orientation

� Good balance of global & local routing� Algorithmic placement & routing with NCL

� Easily scalable� Good for dynamic partial reconfiguration

=TPG=TPG=BUT=BUT=ORA=ORA

Test Session 1Test Session 1Test Session 2Test Session 2

TPGTPG TPGTPG

BUTBUT

BUTBUT

ORAORA

BUTBUT

BUTBUT

ORAORA

BUTBUT

BUTBUT

ORAORA

BUTBUT

BUTBUT

ORAORA

LocalLocalroutingrouting

Global routingGlobal routing

Global routingGlobal routing

LocalLocalroutingrouting

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BISToryBISTory of the ORA (of the ORA (BISToraBISTora))

��ORAsORAs impact BIST architectureimpact BIST architecture��Both logic and routing BISTBoth logic and routing BIST

��ORA design has had big impact on history of ORA design has had big impact on history of BIST for BIST for FPGAsFPGAs��Greater than Greater than TPGsTPGs

��A history of A history of ORAsORAs in BIST for in BIST for FPGAsFPGAscould take a most of a seminar by itselfcould take a most of a seminar by itself��But I donBut I don’’t want to BORA you!!!t want to BORA you!!!

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Latest Logic BIST (Latest Logic BIST (CircularCircular))��Circular comparison of Circular comparison of BUTsBUTs

��Better diagnostic resolutionBetter diagnostic resolution��Possibly better fault detectionPossibly better fault detection

��Need Need TPGsTPGs��Embedded processorEmbedded processor��Other coresOther cores

��DSPDSP��Embedded RAMEmbedded RAM

��DSP counter readsDSP counter reads��RAM (ROM) with test patternsRAM (ROM) with test patterns

��Need sufficient routing resourcesNeed sufficient routing resources��Available in many newer Available in many newer FPGAsFPGAs

=TPG=TPG=BUT=BUT=ORA=ORA

Test Session #1Test Session #2

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Logic BIS

T for Large

Logic BIS

T for Large F

PG

As

FP

GA

s� �

Need to m

anage N

eed to manage

loading on loading on T

PG

sT

PG

s� �

Signals degrade

Signals degrade

completely after 200

completely after 200

PIP

sP

IPs

� �Q

uad BIS

T structures

Quad B

IST

structures in large arraysin large arrays

� �S

mall num

ber of rows

Sm

all number of row

s w

ith BIS

T structure

with B

IST

structure across all colum

nsacross all colum

ns� �

Repeat to fill array

Repeat to fill array

TPGTPGBUTBUTORAORABUTBUTORAORABUTBUTORAORABUTBUTTPGTPGBUTBUTORAORABUTBUTORAORABUTBUTORAORABUTBUT

TPGTPGBUTBUTORAORABUTBUTORAORABUTBUTORAORABUTBUTTPGTPGBUTBUTORAORABUTBUTORAORABUTBUTORAORABUTBUT

TPGTPGBUTBUTORAORABUTBUTORAORABUTBUTORAORABUTBUT


ORAORA



ORAORA



ORAORA



ORAORA



ORAORA



ORAORA

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Other Logic BIST ApproachesOther Logic BIST Approaches��PingPing--Pong (BIST)Pong (BIST)

��One test session by combining One test session by combining TPGsTPGs & & BUTsBUTs��FSM approach with current state as test patternsFSM approach with current state as test patterns

��No No ORAsORAs��ConfigConfig memory memory readbackreadback every BIST clock cycleevery BIST clock cycle

��Only tests Only tests LUTsLUTs and Flipand Flip--flopsflops��More More reconfigsreconfigs in one test sessionin one test session

��BORABORA--BORA (Tahitian BIST)BORA (Tahitian BIST)��One test session by combining One test session by combining BUTsBUTs & & ORAsORAs��No No TPGsTPGs

��Test patterns from embedded processorTest patterns from embedded processor

��Only tests Only tests LUTsLUTs and and FFsFFs

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CAD Tool Features vs. TestabilityCAD Tool Features vs. Testability��Controlling test conditions with CAD toolsControlling test conditions with CAD tools

��Oriented for designOriented for design

��Oriented for synthesisOriented for synthesis

��For testing we need to:For testing we need to:��Control unselected inputs to logic multiplexersControl unselected inputs to logic multiplexers

��Test for stuckTest for stuck--at faultsat faults

��Control opposite logic values on at least one Control opposite logic values on at least one unselected input for MUX unselected input for MUX PIPsPIPs��Test for PIP stuckTest for PIP stuck--on faultson faults

��# test configurations = # MUX inputs# test configurations = # MUX inputs

��DRC complaints about antennas & stubsDRC complaints about antennas & stubs��Delete signals for test conditionsDelete signals for test conditions

AS

B

Zx

sa1

00

11/0 1/0

0

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Logic BIST Place & RouteLogic BIST Place & RoutePAR RoutingPAR Routing

Our Routing HeuristicsOur Routing Heuristics

��Problem:Problem: PAR rePAR re--maps maps BUT configurationsBUT configurations��Supposedly improves routabilitySupposedly improves routability

��Destroys test conditions for fault Destroys test conditions for fault detectiondetection

��Solution:Solution: Develop our own Develop our own routing heuristics in C routing heuristics in C program for logic BISTprogram for logic BIST��Maintains test conditionsMaintains test conditions

��Faster clock frequenciesFaster clock frequencies

��Longer BIST development timeLonger BIST development time

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NCLNCL--XDL Example for ORAXDL Example for ORA

LUT G

BLO1BRO1BLO2BRO2

LUT F

BLO3BRO3BLO4BRO4

LUT H

YQ

inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 ,inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 ,cfg "cfg "F::#LUT:F=(F1@F2)+(F3@F4)F::#LUT:F=(F1@F2)+(F3@F4) F4MUX::F4IF4MUX::F4I

G::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2IG::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2IH::#LUT:H=F+G+H1 H0::G H1::C4H::#LUT:H=F+G+H1 H0::G H1::C4 H2::FH2::FCLKY::CLKCLKY::CLK DY::HDY::H YQMUX::QY SRY::RESETYQMUX::QY SRY::RESET FFY::#FFFFY::#FFSRX::RESET FFX::#FF " ;SRX::RESET FFX::#FF " ;

net "ora_1_1_yq" ,net "ora_1_1_yq" ,outpin "ora_1_1" YQ ,outpin "ora_1_1" YQ ,inpin "ora_1_1" C4 ,inpin "ora_1_1" C4 ,pip R1C1 CENTER_GYQ pip R1C1 CENTER_GYQ --> CENTER_GYQ_VERT ,> CENTER_GYQ_VERT ,pip R1C1 CENTER_GYQ_VERT pip R1C1 CENTER_GYQ_VERT --> CENTER_H2R ,> CENTER_H2R ,pip R1C1 CENTER_H2R pip R1C1 CENTER_H2R --> CENTER_C4 ,> CENTER_C4 ,

;;

routednet inXDL

inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 ,inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 ,cfg "cfg "F::#LUT:F=(F1@F2)+(F3@F4)F::#LUT:F=(F1@F2)+(F3@F4) F4MUX::F4IF4MUX::F4I

G::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2IG::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2IH::#LUT:H=F+G+H1 H0::G H1::C4H::#LUT:H=F+G+H1 H0::G H1::C4 H2::FH2::FCLKY::CLKCLKY::CLK DY::HDY::H YQMUX::QY SRY::RESETYQMUX::QY SRY::RESET FFY::#FFFFY::#FFSRX::RESET FFX::#FF " ;SRX::RESET FFX::#FF " ;

net "ora_1_1_yq" ,net "ora_1_1_yq" ,outpin "ora_1_1" YQ ,outpin "ora_1_1" YQ ,inpin "ora_1_1" C4 ,inpin "ora_1_1" C4 ,

;;

unroutednet in XDL

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Automated BIST ConfigurationsAutomated BIST Configurations��C program generates C program generates

.XDL file.XDL file

�� .XDL converted to .NCD.XDL converted to .NCD��xldxld ––xdl2ncd xdl2ncd bist.ncdbist.ncd

��FPGA EditorFPGA Editor��Design Rule CheckDesign Rule Check

��RouteRoute�� ““no pin swapno pin swap”” optionoption

�� .NCD converted to .BIT .NCD converted to .BIT file to download into file to download into FPGA for BISTFPGA for BIST

FPGA EditorFPGA Editor

BIST ProgramBIST Program

FPGAFPGA

BITgen.exeBITgen.exe

BIT fileBIT file

XDL fileXDL file

NCD fileNCD file

XDL.exeXDL.exe

download

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Programmable Routing NetworkProgrammable Routing Network��Wire segments of varying lengthWire segments of varying length

��xxNN = = NN PLBsPLBs in lengthin length��NN = 1, 2, 4, 6 are common= 1, 2, 4, 6 are common

��xHxH = half the array in length= half the array in length

��xLxL = length of full array= length of full array

��Programmable Interconnect Points (Programmable Interconnect Points (PIPsPIPs))��Also known as Configurable Interconnect Points (Also known as Configurable Interconnect Points (CIPsCIPs))

��Transmission gate connects to 2 wire segmentsTransmission gate connects to 2 wire segments

��Controlled by configuration memory bitControlled by configuration memory bit��0 = wires disconnected0 = wires disconnected

��1 = wires connected1 = wires connected

configbit

Wire A

Wire B

29

PIPsPIPs��BreakBreak--point PIPpoint PIP

��Connect or isolate 2 wire segmentsConnect or isolate 2 wire segments

��CrossCross--point PIPpoint PIP��2 nets straight through2 nets straight through��1 net turns corner and/or fans out1 net turns corner and/or fans out

��Compound crossCompound cross--point PIPpoint PIP��Collection of 6 breakCollection of 6 break--point point PIPsPIPs

��Can route to two isolated signal netsCan route to two isolated signal nets

��Multiplexer PIPMultiplexer PIP��Directional and bufferedDirectional and buffered��Select 1Select 1--ofof--NN inputs for outputinputs for output

��NonNon--decoded MUX PIP decoded MUX PIP –– 1 1 configconfig bit per inputbit per input��Decoded MUX PIP Decoded MUX PIP –– NN configconfig bits select from 2bits select from 2NN inputsinputs

��Major routing resource in new Major routing resource in new FPGAsFPGAs

30

Routing BISTRouting BIST��Program Program PLBsPLBs as as TPGsTPGs and and ORAsORAs

��Like in logic BISTLike in logic BIST��Program groups of wires under testProgram groups of wires under test

��Wire segmentsWire segments��Programmable Interconnect PointsProgrammable Interconnect Points

��Tests partitioned for local and global routing Tests partitioned for local and global routing resourcesresources��Must route through Must route through PLBsPLBs for local routingfor local routing

��Fault modelsFault models�� Bridging faults and opens in wire segmentsBridging faults and opens in wire segments�� Line stuckLine stuck--at faults at faults

�� Shorts to Shorts to VddVdd and and VssVss�� PIPsPIPs stuckstuck--on and stuckon and stuck--offoff

�� Test conditionsTest conditions�� Opposite logic values on wires/Opposite logic values on wires/PIPsPIPs�� Monitor both logic valuesMonitor both logic values

TPG

ORA

PLB

31

First Routing BIST ApproachFirst Routing BIST Approach

��Originally thought logic BIST would Originally thought logic BIST would test routing resourcestest routing resources��Not true (only 55% in ORCA)Not true (only 55% in ORCA)

��ComparisonComparison--basedbased��ORAsORAs compare two groups of compare two groups of WUTsWUTs

��Similar to logic BISTSimilar to logic BIST

��Tried to test as much routing as Tried to test as much routing as possible at one timepossible at one time��Poor diagnostic resolutionPoor diagnostic resolution

��Difficult to develop configurationsDifficult to develop configurations

comparisoncomparison--based ORAbased ORA

WUTsWUTs

TPGTPG

ORAORA

32

Second Routing BISTSecond Routing BIST��Developed during onDeveloped during on--line BIST projectline BIST project

��Testing restricted to routing resources Testing restricted to routing resources for 2 rows or columns of for 2 rows or columns of PLBsPLBs

��Small SelfSmall Self--Test Test AReasAReas ((STARsSTARs))��ComparisonComparison--based BISTbased BIST

��Applied to offApplied to off--line BISTline BIST��Fill FPGA with Fill FPGA with STARsSTARs��Tests run concurrentlyTests run concurrently��Diagnostic resolution to STARDiagnostic resolution to STAR

��Easier BIST developmentEasier BIST development��But more BIST configurationsBut more BIST configurations

��27 vs. 48 for ORCA 2C 27 vs. 48 for ORCA 2C

STARSTAR

WUTsWUTs

TPGTPG

ORAORA

FPGA

TT

OO

TT

OO

TT

OO

TT

OO

TT

OO

33

Other Routing BIST ApproachesOther Routing BIST Approaches

��ParityParity--based based (Sun and Chan)(Sun and Chan)��Xilinx 4000Xilinx 4000

��Parity bit routed over faultParity bit routed over fault--free resourcesfree resources��What is faultWhat is fault--free until youfree until you’’ve tested it?ve tested it?

��Harris and Harris and TessierTessier��Used our comparisonUsed our comparison--based approachbased approach

��Pointed out 2Pointed out 2--testing requirementtesting requirement

��RenovellRenovell and and ZorianZorian��Minimum test configurations for switch boxesMinimum test configurations for switch boxes

��Modified parityModified parity--based approachbased approach

parityparity--based ORAbased ORA

WUTsWUTsparityparity

bitbit

TPGTPG

ORAORA

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Latest Routing BISTLatest Routing BIST��ComparisonComparison--based BISTbased BIST

��No good for small No good for small PLBsPLBs and difficult to routeand difficult to route

��Modified parityModified parity--based approachbased approach��NN--bit upbit up--counter with even parity, counter with even parity, andand��NN--bit downbit down--counter with odd paritycounter with odd parity

��Gives opposite logic values forGives opposite logic values for��StuckStuck--on on PIPsPIPs & bridging faults& bridging faults

��Parity used as test patternParity used as test pattern��NN+1 wires under test+1 wires under test

��Good for small Good for small PLBsPLBs

��Make Make STARsSTARs as small as possibleas small as possible

COCO

Pass/FailPass/Fail

OORRAA

WUTsWUTs

TPGTPGCnCnParPar

+

35

Our FPGA BIST ConfigurationsOur FPGA BIST Configurations

15215212812812124000E/Spartan4000E/Spartan23023020620612124000XL/XLA4000XL/XLA3073072832831212VirtexVirtex--I/SpartanI/Spartan--IIII

6464565644AT94K/40KAT94K/40KAtmelAtmel459459419419202039K39KCypressCypress

XilinxXilinx

ORCAORCA

FPGAFPGA

??

76766666

TotalTotal

??1515VirtexVirtex--44

484814142CA2CA27 (48)27 (48)992C2C

RoutingRoutingLogicLogic

Notes: Logic BIST configurations are applied 2 timesConfigurations for embedded cores not included

36

Comparing Comparing FPGAsFPGAs��Routing BISTRouting BIST

��Routing resources per PLBRouting resources per PLB��4000XL/XLA has 25% more than ORCA 2C/2CA4000XL/XLA has 25% more than ORCA 2C/2CA

��ORCA 2C/2CA has 48% more than 4000E/SpartanORCA 2C/2CA has 48% more than 4000E/Spartan

��Routing BIST configurationsRouting BIST configurations��206 for 4000XL/XLA206 for 4000XL/XLA

��48 for ORCA 2C/2CA48 for ORCA 2C/2CA

��128 for 4000E/Spartan128 for 4000E/Spartan

��Number and size of multiplexer Number and size of multiplexer PIPsPIPs��NN=5 for ORCA 2C multiplexer =5 for ORCA 2C multiplexer PIPsPIPs

��NN=35 for 4000XL/XLA multiplexer =35 for 4000XL/XLA multiplexer PIPsPIPs

��Bad News:Bad News: more & larger MUX more & larger MUX PIPsPIPs in new in new FPGAsFPGAs��Even more routing BIST configurationsEven more routing BIST configurations

37

Comparing Routing ArchitecturesComparing Routing Architectures��PLB input/output access to bussesPLB input/output access to busses

��More difficulty routing to/from wires = more More difficulty routing to/from wires = more configsconfigs

��Shared vs. dedicated busses to each PLBShared vs. dedicated busses to each PLB��Routing conflicts from TPGs to ORAs = more Routing conflicts from TPGs to ORAs = more configsconfigs

long lineslong lines byby--1 lines1 lines byby--4 lines4 lines

SB SB

SBSB

FGC1FGC2

FGC3FGC4

X/XQ

Y/YQXilinxXilinx

F1-4G1-4C1-4

O1-4

ORCAORCA

repeatersrepeaters

AtmelAtmel

38

Current R&DCurrent R&D��Use embedded processor core to Use embedded processor core to

��Reconfigure FPGA for BISTReconfigure FPGA for BIST��Execute BIST and retrieve BIST resultsExecute BIST and retrieve BIST results��Perform diagnostic procedurePerform diagnostic procedure��Perform fault injection emulationPerform fault injection emulation

��Methodical verification of BIST configurationsMethodical verification of BIST configurations

��Processor must access configuration memoryProcessor must access configuration memory��Configuration memory read very helpfulConfiguration memory read very helpful

�� Implemented in Atmel AT94KImplemented in Atmel AT94K��88--bit AVR microcontrollerbit AVR microcontroller��Configuration memory write access onlyConfiguration memory write access only

��Currently implementing in VirtexCurrently implementing in Virtex--4 for NSA4 for NSA��PowerPC (hard core) & PowerPC (hard core) & MicroBlazeMicroBlaze (soft core)(soft core)��Configuration memory write and read accessConfiguration memory write and read access

39

Logic BIST Architecture Logic BIST Architecture -- VirtexVirtex II ProII Pro

Logic BISTLogic BISTCircuitryCircuitry

Embedded Embedded ProcessorProcessor

��4 Test Sessions 4 Test Sessions ��Right Half Right Half –– East & WestEast & West

��Left Half Left Half –– East & WestEast & West

��Circular comparison for Circular comparison for better diagnosisbetter diagnosis��TPG incorporated in the TPG incorporated in the

processor half of FPGAprocessor half of FPGA

��Replace TPG column with Replace TPG column with ORAsORAs

��Extra routing needed for Extra routing needed for BUTBUT--toto--ORA connections ORA connections at edgeat edge

40

Test Time Results for AT94KTest Time Results for AT94K

182.4182.40.110 sec0.110 sec20.064 sec20.064 secDownloadDownload0.0750.0750.343 sec0.343 sec0.026 sec0.026 secExecutionExecution

76.076.00.101 sec0.101 sec7.680 sec7.680 secDownloadDownload0.20.20.085 sec0.085 sec0.016 sec0.016 secExecutionExecution

43.543.50.639 sec0.639 sec27.786 sec27.786 secTotal Test TimeTotal Test Time20.090 sec20.090 sec

7.696 sec7.696 sec

DownloadDownload

0.453 sec0.453 sec

0.186 sec0.186 sec

ProcessorProcessor

44.344.3Total timeTotal time

Routing Routing BISTBIST

41.441.4Total timeTotal time

Logic Logic BISTBIST

SpeedSpeed--upupFunctionFunctionResourceResource

��60 BIST configurations60 BIST configurations

��Maximum download clock frequency = 1MHzMaximum download clock frequency = 1MHz

��Maximum processor clock frequency = 25 MHzMaximum processor clock frequency = 25 MHz

41

Memory Reduction ResultsMemory Reduction Results

��Download approach needs 3.5 Download approach needs 3.5 MbyteMbyte for storagefor storage��Requires external control for BIST and diagnosisRequires external control for BIST and diagnosis

��ProcessorProcessor--generated BIST programgenerated BIST program�� Includes all control and diagnostic routinesIncludes all control and diagnostic routines

��Will fit in program memory of embedded processorWill fit in program memory of embedded processor

��Or can be easily downloaded when neededOr can be easily downloaded when needed

1581581122 Kbyte22 Kbyte606058 Kbyte58 KbyteCombinedCombined1791791114 Kbyte14 Kbyte444457 Kbyte57 KbyteRoutingRouting80801112 Kbyte12 Kbyte161660 Kbyte60 KbyteLogicLogic

# # FilesFilesFile SizeFile Size# #

FilesFilesAverageAverageFile SizeFile Size

Memory Memory Reduction Reduction

FactorFactor

ProcessorProcessorDownloadDownloadResourceResource

TestedTested

42

SummarySummary��Growing use of FPGAs in systems and Growing use of FPGAs in systems and SoCsSoCs

��FPGA testing is necessary but difficult due toFPGA testing is necessary but difficult due to��ProgrammabilityProgrammability

��Complex interconnect networkComplex interconnect network��Logic BIST is simple compared to routing BISTLogic BIST is simple compared to routing BIST

��Constantly growing size and changing architecturesConstantly growing size and changing architectures

�� Incorporation of new and different coresIncorporation of new and different cores

��Test development is time consumingTest development is time consuming��New FPGA capabilities help BISTNew FPGA capabilities help BIST

��Dynamic partial reconfiguration and Dynamic partial reconfiguration and readbackreadback��Configuration by processor coresConfiguration by processor cores

The BIST History of FPGAs The BISTory of FPGAsagrawvd/D&TSEMINAR_SPR06/SLIDES... · The BIST...

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