3-4 Sept. 2008 EFW INST+SOC PDR 1

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RBSPElectric Field and Waves Instrument

(EFW)

Instrument Data Processing Unit (IDPU)

Preliminary Design Review

Michael Ludlam

Space Sciences Laboratory

UC Berkeley

2 3-4 Sept. 2008 EFW INST+SOC PDR

EFW – IDPU

– Introduction

– Requirements

– Block Diagram

– Board Overview

– Specifications

– Heritage

– Spacecraft & Inter-board Interfaces

– Backplane

– Shielding

– Resources

– I&T

– Schedule

– Personnel

3 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Introduction

– Scope of Presentation• Gives overview of Instrument Data Processing Unit (IDPU).• Areas that are handled at the IDPU top level are discussed in detail here.• Individual board details, requirements and designs are discussed during those

board presentations.

– Synopsis: IDPU houses most of the instrument electronics, providing the electrical interface between the spacecraft and the sensor / boom units. It contains four circuit boards:

• Low Voltage Power Supply (LVPS) and Power Control Board Circuit (PCB)• Digital Control Board (DCB) • Digital Fields Board (DFB)• Boom Electronics Board (BEB)

4 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Requirements

• Requirements for IDPU are derived from the EFW System Requirements (RBSP_EFW_SYS_001_Requirements)

• Only requirements that are directly relevant to the IDPU as a unit are reported here. Individual board level requirements are detailed in appropriate presentations.ID Req. Title Subject Prio rity Requirem ent B o dy o r Sectio n Heading

Verificatio n

Metho dVerificatio n Planning No tes

EFW-1 Instrument Design lifeEach EFW Instrument

shallbe designed for a total lifetime duration of 2 years plus 60 days. A

Analyses of limited life items and consumables , parts radiation tollerance, parts reliability

EFW-22Functionally Identical EFW Instrument Suites

Each EFW Instrument

shallbe functionally identical.

T Calibrations , CPT

EFW-23EFW - Spacecraft ICD Compliance

Each EFW Instrument

shall

comply with the EFW-to-Spacecraft interface control documents (ICDs). T CPT, FSW Tes ts

EFW-55EFW Instrument Data Processor Unit

Each EFW IDPU

shall

house and provide EMC closeout, thermal control, and radiation protection to the following: boom electronics , a/d circuitry, E-Field buffers , computer and solid s tate recorder, power controller, and power converter.

I, A, T EMC Tes t, Thermal vac tes t

EFW-63 EFW Main Power AllocationEach EFW Instrument

shallnot exceed the total power of 11.16W from the EFW Main 28V Service

T CPT

EFW-75EFW IDPU Operational Temp Range

The EFW IDPU shall perform as designed from -25 to +55C (TBR) T Thermal Vac

EFW-78EFW IDPU Survival Temp Range

The EFW IDPU shall survive without damage from -30 to +60C (TBR) T Thermal Vac

EFW-88 EFW IDPU ICD Compliance The EFW IDPU shallcomply with the requirements and constraints imposed by all relevant instrument-to-spacecraft interface control documents (ICDs).

I,T CPT, functionals

EFW-104 EFW IDPU Mass The EFW IDPU shall not exceed 10.37 kg (TBR) T Mass Properties

EFW-131EFW Initial Power On/Reset State

The EFW IDPU shallpower up in a nominal condition for measuring E-Fields without processor intervention.

T CPT

5 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Block Diagram

6 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Board Overview

– IDPU Contains 4 Boards:

• LVPS & PCB (SSL) – Power supply and switching. Receives power from S/C and converts it to board required voltages. Converters all synchronized together at one frequency. Boom deployment voltages are S/C provided but switched on the PCB circuit.

• DCB (SSL) – Processor Board, Memory and S/C Digital Interface. Accepts and responds to incoming S/C commands and sends Housekeeping and compressed Science Data in Telemetry stream. On card memory stores data received from DFB.

• DFB (LASP) – Analog and Digital Signal Processing. Processes signals from sensors and digitizes them to produce waveform and spectral products that are sent to the DCB board.

• BEB (SSL) – Boom Sensor Control. Supplies bias current and control voltages to set the sensors to the correct operating regime.

7 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Electrical Specifications

– Board Specification Documents:

• RBSP_EFW_LVPS_001E_Specification• RBSP_EFW_DCB_003C_Specification• RBSP_EFW_DFB_001A_SPECrev2_04_25_08• RBSP_EFW_BEB_001B_Specification• RBSP_EFW_BPL_001G_Specification

8 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Heritage

– RBSP IDPU is heavily based on the successful THEMIS IDPU, failure free in orbit combined operation for over 7 years. THEMIS IDPU itself was based on a long history of instrumentation at SSL/UCB.

Board Most Recent Heritage NotesLVPS / PCB Themis Same Topolgy as Themis

DCB ThemisVery similar design, new Actel containing processor, Flash memory, new S/C interface

DFB Themis Very similar design, new Actel, buffers added to receive EMFISIS signals

BEB Themis

Almost Identical Layout, Changes to components to drive preamp +/-225V. No FPGA, added buffers to supply signal to EMFISIS

THEMIS IDPU

9 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU External Electrical Interfaces

• IDPU provides interface to S/C via:– 1 x 15M DSub Connector on the LVPS (Instrument and Boom Deploy Power).– 1 x 9F DSub Connector on the DCB (Instrument Commands, 1PPS/SP, Instrument

Telemetry).– Interfaces are defined in the APL Controlled EFW ICD (7417-9083) – currently

RevB.– low level signals have been verified by APL provided GSE.

• IDPU provides interface to boom units via:– 3 x 26F HDSub Connectors on the BEB board (Defined in BEB Specification –

RBSP_EFW_BEB_001).– 1 x 62F HDSub Connector on the LVPS/PCB board (Defined in LVPS/PCB

Specification – RBSP_EFW_LVPS_001).– Verified during instrument I&T.

• IDPU provides interface to EMFISIS via:– pins on 3 x 26F HDSub Connectors on BEB Board (EFW out).– 1 x 26M HDSub Connector on DFB (FGM, SCM in).– Interfaces are defined in the APL Controlled EFW to EMFISIS ICD (7417-9089) –

currently RevD.– Verified by EFW – EMFISIS interface test.

10 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Internal Electrical Interfaces

– IDPU Boards plug into a backplane board that provides board to board connections – power, command, telemetry, and housekeeping.

– Digital board to board interfaces are:• DCB – DFB : UCB ‘CDI’ interface – serial data protocol for command and

telemetry using a common clock.• DCB – BEB : Controls DACs via command, clock and latch lines, muxes with

bi level control signals, test signal (AC Test) – 2 lines.• DCB – PCB : Command, Clock and Strobe line control decoders on PCB

circuit.

THEMIS Backplane – note different number of connectors.

THEMIS IDPU Backplane

11 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Backplane

– IDPU Backplane schematics are complete.

– Layout is waiting on final board spacing inside the IDPU box. Once this is finalized the board can go to layout.

– All pins are connected, or tied to ground (no floating pins).

– Card uses two types of connector (DIN96, Hypertronics 80pin) both flown on THEMIS.

– Initial board to board tests use a GSE backplane that is mounted in a standard VME 19” rack.

12 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Telemetry Flow diagram

DFB SDRAM

FLASH

FSW

S/C I/F80kbs

S/C8.38Mbs

Configuration Commands

512

Pac

ket

Hea

ders

/s

>10Mb/s>10Mbs

256 Packets/s

Flowchart shows the capability of telemetry flow from DFB to S/C.

System is able to handle maximum data rate from DFB.

Limiting factor is interface to S/C.

8.38Mbs

Ground Commands

HK

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gnos

tics

13 3-4 Sept. 2008 EFW INST+SOC PDR

Shielding

• Provision is made for EMC/EMI board shields on the LVPS, DCB and DFB.

• No radiation spot shielding is anticipated on any IDPU board – radiation shielding is done at box level (covered by IDPU Mechanical Design presentation).

LVPS Shield

DCB ShieldDFB Shield

BEB Board

14 3-4 Sept. 2008 EFW INST+SOC PDR

IDPU Power

• All power for EFW is routed through the IDPU, including that to deploy booms.

• The supplies for the IDPU (PCB, DCB and DFB) and the BEB are independent that allows the BEB to function in the event of failure on another IDPU board and still provide EMFISIS with boom sensor signals.

Pwr +5V D +1.8V D +3.6D (1) +5V A -5V A +10VA -10VA +5V D +10V A -10V A +225V -225V +/-15F1 +/-15F2 +/-15F3 +/-15F4 +/-10F5 +/-15F6 +28V P +5V P

EFIRadial Unit 1 0.120 0.004 0.100 2.000

Radial Unit 2 0.120 0.004 0.100 2.000Radial Unit 3 0.120 0.004 0.100 2.000

Radial Unit 4 0.120 0.004 0.100 2.000Axial Unit 1 0.120 0.004 0.903Axial Unit 2 0.120 0.004 0.903

DPU[4] DFB Fast Survey 1.463 0.008 0.190 0.060 0.050 0.066 0.016 0.013

[5] AC Buffers 0.360 0.018 0.018[5] BEB 1.120 0.016 0.026 0.015 0.001 0.001 0.002 0.002 0.002 0.002 0.002 0.002[2] PCB 0.488 0.003 0.005 0.025 0.020

[3] SSR 0.072 0.020

[3] DCB 1.111 0.020 0.250 0.149 0.001 0.001 0.001 0.001[1] LVPS 3.595 0.015 0.242 0.126 0.029 0.039 0.023 0.019 0.009 0.024 0.018 0.002 0.002 0.003 0.003 0.003 0.003 0.003 0.003

Instrument TOTAL 8.927 5 1.8 3.6 5 5 10 10 5 10 10 225 225 30 30 30 30 30 30 VOLTAGES

Avg 0.028 0.440 0.228 0.053 0.071 0.042 0.034 0.016 0.044 0.033 0.001 0.001 0.006 0.006 0.006 0.006 0.006 0.006 CURRENT

0.14 0.79 0.82 0.26 0.36 0.42 0.34 0.08 0.44 0.33 0.14 0.14 0.18 0.18 0.18 0.18 0.18 0.18 POWER

BEBIDPU

Instrument VoltagesCalc by Voltage

Average Power

15 3-4 Sept. 2008 EFW INST+SOC PDR

Mass Resources

• IDPU Mass is 8.29kg (CBE) and has a NTE of 10.37kg (25%)

• IDPU board mass estimates are based on THEMIS equivalent boards and appropriately updated (extra circuitry on DCB, BEB etc).

ComponentUnit

Mass(kg)

CBEMass(kg)

Radshield(kg)

CBEw/ shield

%

growthAGM

NTEMass(kg)

IDPU 6.01 6.01 2.28 8.29 25% 10.37DFB 0.438 0.438 0.000 0.438 25% 0.548

BEB+BFR 0.508 0.508 0.000 0.508 25% 0.635

DCB+ALBM 0.469 0.469 0.000 0.469 25% 0.586

LVPS 0.646 0.646 0.000 0.646 25% 0.807

Backplane 0.130 0.130 0.000 0.130 25% 0.163

Chassis 3.824 3.824 2.280 6.104 25% 7.630

Top 1.120 1.120 0.000 1.120 25% 1.400

Bottom 1.162 1.162 0.000 1.162 25% 1.453

Front 0.172 0.172 0.000 0.172 25% 0.215

Back 0.530 0.530 0.000 0.530 25% 0.663

Left 0.420 0.420 0.000 0.420 25% 0.525

Right 0.420 0.420 0.000 0.420 25% 0.525

Removable Shield Delta 0.000 0.000 2.280 2.280 25% 2.850

CBE Mass

16 3-4 Sept. 2008 EFW INST+SOC PDR

Subsystem Testing

• IDPU I&T Flow:– Individual IDPU boards delivered to IDPU for integration once they have

met board requirements.

– Board to board interfaces are then verified.

– Integration will follow written test procedure.

– Unit is assembled in box and functionally tested (e.g. CPT).

– IDPU then ready for IDPU level FSW testing, IDPU to SPB/AXB testing or IDPU environmental tests.

– Further I&T descriptions are dealt in I&T presentation.

17 3-4 Sept. 2008 EFW INST+SOC PDR

Personnel

• LVPS & PCB : Peter Berg (SSL)

• DCB : Michael Ludlam & Dorothy Gordon (SSL)

• FSW : Peter Harvey (SSL)

• DFB : Wesley Cole, Ken Stevens, Susan Batiste (LASP)

• BEB : Jane Hoberman (SSL)

• IDPU : Michael Ludlam, Rachel Hochman (SSL)

• CHASSIS : William Donakowski (SSL)

• GSE : William Rachelson (SSL)

• PARTS: Ron Jackson & Jorg Fischer (SSL)

18 3-4 Sept. 2008 EFW INST+SOC PDR

Schedule

IDPU Schedule is kept up to date and reported monthly.

Key Dates:

LVPS ETU Ready: 12/22/08

DCB ETU Ready: 12/29/08

DFB ETU Delivered to UCB: 1/21/09

BEB ETU Ready: 1/5/09

ETU IDPU delivery to I&T: Feb 09

F1 IDPU delivery to I&T: Oct 09

F2 IDPU delivery to I&T: Nov 09

3-4 Sept. 2008 EFW INST+SOC PDR 19

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RBSPElectric Field and Waves Instrument

(EFW)

Data Control Board (DCB)

Preliminary Design Review

Michael Ludlam

Space Sciences Laboratory

UC Berkeley

20 3-4 Sept. 2008 EFW INST+SOC PDR

Data Control Board

– Introduction

– Requirements

– Block Diagram

– Specification

– Board Overview

– Design

– Interfaces

– Heritage

– Resources

– Breadboard

– ETU

– Parts

– Schedule

RBSP DCB Breadboard

21 3-4 Sept. 2008 EFW INST+SOC PDR

DCB Introduction

– Scope of Presentation• Gives overview of DCB board.• DCB FPGA Actel presentation follows and is only presented as a component

in this presentation.• EFW FSW is detailed in a separate presentation.

– Synopsis: The DCB card; • provides the digital interface between the S/C and the rest of the instrument.• receives, packetizes and stores science data before transmitting it to the

spacecraft. • receives and transmits housekeeping to the spacecraft.• receives and acts on commands from the spacecraft.

22 3-4 Sept. 2008 EFW INST+SOC PDR

Requirements

ID Req. Title Subject Prio rity Requirem ent B o dy o r Sectio n HeadingVerificatio n

Metho dVerificatio n Planning No tes

EFW-60 EFW Data ProcessingEach EFW IDPU

shallcontain a processor and solid-s tate recorder capable of recording and playing back E-Field and B-Field data D C PT

EFW-81 EFW Command The EFW IDPU shallaccept commands via serial interface

T CPT

EFW-82 EFW Telemetry Rate The EFW IDPU shallgenerate a continuous, serial telemetry stream at a rate not to exceed 12,000 bps.

T CPT

EFW-83 EFW Telemetry Peak The EFW IDPU shalllimit the instantaneous data rate to the spacecraft to ≤80 kbps

T CPT

EFW-84 EFW Telemetry Compression The EFW IDPU shallperform data compression

T CPT

EFW-85 EFW use of MET The EFW IDPU shalluse Mission Elapsed Time (MET) as the reference time for time stamps produced for science, space

T CPT

EFW-86 EFW MET Acceptance The EFW IDPU shallaccept the distribution of MET from its respective spacecraft at a frequency of 1 Hz.

T CPT

EFW-87 EFW Serial Interface The EFW IDPU shall

accommodate a standard point-to-point serial interface for data exchange with the spacecraft.

T CPT

EFW-97 EFW Data Integrity The EFW IDPU shalldetect and correct data errors in its Solid State Recorder.

T CPT

• DCB only requirements are listed. FSW requirements are covered in FSW presentation.

23 3-4 Sept. 2008 EFW INST+SOC PDR

EFW Block Diagram

24 3-4 Sept. 2008 EFW INST+SOC PDR

Board Overview

• Actel FPGA contains CAST IP Z80 core. Processor clocked at 16.77 MHz (224Hz).

• Software is stored in PROM (32kB) and EEPROM (128kB) and transferred to SRAM (128kB) on boot.

• Data is stored in SDRAM (256MB) and FLASH (32GB) that are on private buses.

• Commands are received on the S/C interface and acted on by the FSW.• Inter-board communication is controlled by the DCB, using a slightly different

interface for each board (detailed in IDPU presentation). • Data is received on two lines from the DFB and stored directly to SDRAM

using DMA channels in the FPGA.• Burst data is transferred to and from the FLASH memory from SDRAM.• Housekeeping is received on the backplane and on board and multiplexed

into a single ADC. • Telemetry (Science Data and Housekeeping) is sent to the S/C using LVDS

interface. • Circuit fits on single 6U card (233mm x 160mm)

25 3-4 Sept. 2008 EFW INST+SOC PDR

DCB Block Diagram

26 3-4 Sept. 2008 EFW INST+SOC PDR

DCB Specifications

– DCB Board Specification Document:

• RBSP_EFW_DCB_003C_Specification

– DCB FPGA Specification Document:• RBSP_EFW_DCB_001F

– FSW Specification Document:• RBSP_EFW_FSW_003_Specification

27 3-4 Sept. 2008 EFW INST+SOC PDR

Interfaces

– DCB has digital interface to S/C via 9F DSub Connector (Instrument Commands, 1PPS/SP, Instrument Telemetry).

– Interface is defined in the APL Controlled EFW ICD (7417-9083) –currently RevB.

– Signal levels have been verified by APL provided GSE.

– DCB also has an external 51-way connector to help during I&T. Connector cover will be installed on delivery of IDPU to APL.

– Internal IDPU communications are routed on the 96pin DIN connector that connects to the backplane.

28 3-4 Sept. 2008 EFW INST+SOC PDR

Heritage

– Heritage• DCB is based on THEMIS equivalent board (also called the DCB).• Much of the FPGA logic is the same (converted from schematics to VHDL).• Although processor is different (RBSP: Z80, THEMIS: 8085) instruction set is

compatible and allows reuse of FSW modules.• SDRAM is identical to one flown on THEMIS.• SRAM, EEPROM are 3.3V equivalent parts of those flown on THEMIS.• ADC & Mux are identical to ones flown on THEMIS.• Regulator (3.3V & 1.5V) is based on design used on THEMIS.

– New• IP Core – prototyped on breadboard.• Flash – prototyped on breadboard.• LVDS – tested on breadboard, APL recommended parts.

29 3-4 Sept. 2008 EFW INST+SOC PDR

Resources

– Mass CBE 469g, NTE 586g (Includes 25% margin).

– Power CBE 1.18W, NTE 1.48W (Includes 25% margin).

Heritage Level Allowance W Reserve NTE W +5V D +1.8V D +3.6D (1) +5V A -5V A +10VA -10VA

[3] DCB Themis Concept 25% 1.18 25.00% 1.48 1.183 0.020 0.250 0.169 0.001 0.001 0.001 0.001

Instrument PowerContingency Pwr Current for Individual Voltage Supplies (Amps)

30 3-4 Sept. 2008 EFW INST+SOC PDR

Breadboard DCB

• During Phase B and breadboard circuit was built up to test new developments: IP Core inside FPGA and Flash memory.

• Board will also act as good test environment while engineering unit is being built up over next few months.

Flash Based FPGA

External Z80 (so far not needed)

PROM EEPROM SRAM

SDRAM

FLASH Memory

S/C Interface

ADC

31 3-4 Sept. 2008 EFW INST+SOC PDR

Breadboard Testing Results

• Processor has worked extremely successfully in FPGA. Good support from vendor. Very useful to be able to simulate processor in FPGA simulation program (ModelSim).

• Flash memory cannot be cold spared.

• SDRAM, PROM, EEPROM and SRAM have been successfully tested.

• ADC successfully tested.

• S/C Interface tested

• Method to download code to breadboard has worked well.

• Breadboard testing of regulator and Flash/SDRAM switches is being tested on a separate board.

32 3-4 Sept. 2008 EFW INST+SOC PDR

DCB ETU

• Schematics are nearly complete for the ETU, recent changes are being implemented.

• Layout will start as soon as schematics are complete.

• ETU will use engineering versions of all the flight parts.

• Initial prototyping of the FPGA will be done with a reprogrammable flash FPGA (same as breadboard) on a socket.

• Initially, PROM will be replaced with EEPROM.

33 3-4 Sept. 2008 EFW INST+SOC PDR

DCB ETU Layout

Proposed major component placements

34 3-4 Sept. 2008 EFW INST+SOC PDR

IC Parts List & Status

• FPGA – Part is being procured by APL for UCB. Space Qualified Actel. • PROM / EEPROM / SRAM – All parts meet TID / SEE Immune (up to 80 MeVcm2/mg)• SDRAM – Flown on THEMIS. Approved for use by APL. Rad Tolerant and SEE

Immune (up to 80 MeVcm2/mg).• FLASH – Meets TID and APL happy with SEU data, APL approved waiver with

proposed use strategy to deal with SEFI performance.• ADC – Meets TID, APL approved waiver for SEU.• LVDS – APL recommended part used.

Component Manufacturer Part No QuantityFPGA Actel RTAX2000S (PROTO) /A3P1000 1Prom BAE 238A790 / AT28BV256 1EEProm Maxwell 28LV010 1SRAM Honeywell HLX6228 1SDRAM 3d-Plus MMSD08256804S-C-1S 1Flash 3d-Plus MMFN08408808S-F-1S 8Buffers Aeroflex UT54ACS164245S 19ADC Linear LTC1604 1Mux Intersil HI-0508 1LVDS Receiver Aeroflex UT54LVDS032LV 1LVDS Driver Aeroflex UT54LVDS031LV 1

35 3-4 Sept. 2008 EFW INST+SOC PDR

Schedule

DCB progress is tracked in the IDPU Schedule.

Task Completion Date

ETU Schematics 9/5/08

ETU Layout 9/26/08

Board Fabrication 10/10/08

Board Assembly 10/24/08

Test 11/21/08

Board to IDPU Dates: ETU 12/29/08

F1 7/31/09

F2 8/14/09

36 3-4 Sept. 2008 EFW INST+SOC PDR

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