2-10-2010-1-

Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures

Chenming Hu and Je Min Park

Univ. of California, Berkeley

2-10-2010-2-

Outline

• Introduction ▪

Background and Motivation

• MOSFETs with Vacuum-Spacer

• Vacuum-Corridor Interconnects

2-10-2010-3-

Reducing Capacitance is Important for Speed

0.01 0.1 1Gate Length, Lgate (um)

0.1

1

10

100

1000

c lass ic sca lin g

T ox (C )

V d d (V )

V t (V )

TOX (Å)

VDD (V)

VTH (V)

B. Meyerson, IBM, Semico Conf., January 2004

CVI

Delay ∝ ∝Q

I

2-10-2010-4-

Reducing Capacitance is Good for Swiching Energy and Noise

Cm

CV2Energy ∝ Crosstalk Noise

Cm∝

10.10.011

10

100

1000

Gate Length (μm)

Po

wer

(W/

cm2)

B. Meyerson, IBM, Semico Conf., January 2004

Metal Lines

2-10-2010-5-

Outline

• Introduction

• MOSFETs with Vacuum-Spacer ▪

Structure, benefits, process ▪

Self-Aligned Contact (SAC) MOSFET

• Vacuum-Corridor Interconnects

• Future Works

2-10-2010-6-

1996 Air-Gap Structure

There is only 6% inverter speed improvement

▪

The fringing capacitance is much smaller than other gate capacitances

▪

Relatively small portion of air-gap (15nm)

P

Air-gap

M. Togo, VLSI 1996

2-10-2010-7-

Gate Capacitances

Gate-channel capacitance

Gate overlap capacitance

Junction/Diffusion capacitance

Fringing capacitance

Gate-to-Contact capacitance

Gate

Source Drain

Contact

2-10-2010-8-

Vertical Scale Down is Difficult

Gate shape

Ideal Scaling

Real Scale Down

Gate Height

Gate Length

2-10-2010-9-

CGC becomes the Dominant Capacitance in Transistor

CGCCGOX

Gate

Contact

» CGC<

CGOX : Gate Oxide Capacitance

CGC : Gate-to-Contact Capacitance

Scale Down

CGOX

2-10-2010-10-

IDS -VGS Characteristics are Same

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

0 0.2 0.4 0.6 0.8 1VGS(V)

IDS(A

/um

)

Conventional Oxide SpacerAir Spacer

VDS=1.0V

Oxide Spacer

Vacuum SpacerGate

Contact

A vacuum spacer transistor is compared with an oxide spacer transistor at 20nm gate length

2-10-2010-11-

Gate Capacitances and switching Charges are Reduced

Oxide Spacer

Vacuum Spacer

QGATE fC/um2

26 19.2

0

5

10

15

20

25

30

35

40

0 0.2 0.4 0.6 0.8 1

VGS(V)

CG

ATE(f

F/

um

2)

Air Spacer

Oxide Spacer

VDS

= 1V

CV2 Energy ∝= QV

2-10-2010-12-

3D Mixed-Mode Device Simulation

dtIV DDDD Extract Propagation Delay

Inverter Switching Energy :

IDD

VIN VOUT

CL

VDD

Miller Capacitances

2-10-2010-13-

Vacuum Spacer CMOS is faster than Oxide Spacer CMOS

-0.25

0

0.25

0.5

0.75

1

1.25

0 1E-11 2E-11 3E-11 4E-11 5E-1Time (s)

Vo

ltag

e (

V)

Oxide SpacerVacuum Spacer

6.1ps

4.7ps

2-10-2010-14-

Gate Spacer Comparison

Air spacer is compared with nitride spacer and oxide spacer

Nitride Spacer

Oxide Spacer

Vacuum Spacer

ION mA/um 1.16 1.06 1.06

IOFF nA/um 4.16 5.55 5.64

Inverter Delay, ps

6.9(1.12)

6.15(1)

4.7(0.76)

Inverter switching energy, fJ

29.5(1.22)

24.2(1)

18.1(0.75)

Nitride Spacer

Contact

2-10-2010-15-

The Benefits of Vacuum Spacer in Future Linear Contact are Greater

Future contact may be linear, not circular

Nitride Spacer

Oxide Spacer

Air Spacer

Inverter Delay, ps

Circular 6.9(1)

6.15(0.89)

4.7(0.68)

Linear 5.96(1)

4.64(0.78)

3.28(0.55)

Inverter switching energy,

fJ

Circular 29.5(1)

24.2(0.82)

18.1(0.61)

Linear 37.2(1)

29.8(0.80)

20.1(0.54)

Linear Contact

Circular Contact

2-10-2010-16-

Process Flow

(a) After S/D formation

(c) Chemical Mechanical Polishing

(b) ILD deposition

(d) Sacrificial spacer removal

(e) ILD2 deposition

Substrate

Source/Drain

Gate

Oxide

Sacrificial spacer

Jemin Park et. al., “Air Spacer MOSFET Technology for 20nm Node and Beyond”, IEEE ICSICT, Oct. 2008, p53-56

Mask Oxide

ILD1

Sacrificial Spacer

Air Spacer

ILD2

2-10-2010-17-

SOI Thinning

Fabrication in Progress

Alignment Mark

400

500

600

700

800

900

1000

1100

#1 #2 #3 #4 #5 #6 #7 avg

Wafer number

Th

ick

ne

ss (

A)

TCBLRTLTRBLBRAVGTafterCafterBafterLafterRafterTlafterTrafterBlafterBrafterAVGafter

Before SOI Thinning

After SOI Thinning

Oxidation condition (Tystar2): 900℃, O2 4000sccm, oxidation 600min, post anneal 20min

Active Patterning

2-10-2010-18-

Another Style of Contact Design, Self-Aligned Contact

Self-Aligned ContactConventional Contact

Gate

Contact

Perfect Alignment

Misaligned

Gate

Contact

WSi2

Poly-Si

Silicon Nitride

Contact

2-10-2010-19-

SRAM size can be reduced with SAC

Intel 45nm SRAM Cell Imaginary Design using SAC

Design Rule : F Cell Width : 10F Cell Height : 5F Cell Area : 50F2

Design Rule : F Cell Width : 10F Cell Height : 3.5F Cell Area : 35F2

Intel Tech. Journal, Vol. 12, 2008

Contact Contact

Gate

Active

2-10-2010-20-

Proposed Process Procedure of SAC with Vacuum Spacer

Substrate

Source/Drain

Gate

Oxide

Nitride

Contact

(a) Gate stack deposition

(b) Gate etch and sidewall oxidation

(c) S/D and spacer formation

(d) ILD deposition and CMP

(e) SAC etch and contact plug deposition

(f) CMP and remove nitride material (g) ILD2 deposition

Air Spacer

Jemin Park et. al., “Air-Spacer Self-Aligned Contact MOSFET for Future Dense Memories”, IEEE SISPAD, Japan, Sep. 2008, p53-56

2-10-2010-21-

(a) After CMP Process

Substrate

Source/Drain Gate

ILD

Sacrificial Spacer

GOX

Sacrificial Gate

Contact

(b) Remove sacrificial gate and form gate stack

(c) Top sacrificial spacer formation

(d) ILD deposition and SAC formation

(e) Remove sacrificial spacers

(f) ILD2 Deposition

Jemin Park et. al., “Gate Last MOSFET with Air Spacer and Self-Aligned Contacts for Dense Memories”, IEEE VLSI-TSA, Taiwan, Apr. 2009, p105-106

Gate Last Process with SAC and Vacuum Spacer

Air Spacer

2-10-2010-22-

Oxide Spacer

Nitride SAC

Air SAC

ION mA/um 1.06 1.13 1.08

IOFF nA/um 5.55 2.56 6.14

Inverter Delay, ps

6.15(1)

11.85(1.93)

5.05(0.82)

Inverter switching energy, fJ

24.2(1)

44.8(1.85)

18.8(0.78)

Relative Area 1 0.7 0.7

SAC MOSFET with vacuum spacer is denser, faster, lower energy than a conventional MOSFET, 20nm.

The Case for Vacuum Spacer SAC

Oxide Nitride

Air

2-10-2010-23-

10

25

40

55

70

20 32 45 65Gate Length (nm)

Sw

itch

ing E

ner

gy

(fJ)

25

35

45

55

65

Imp

rovem

en

t (%

)

6

8

10

12

14

20 32 45 65Gate Length (nm)

Del

ay T

ime

(ps)

15

20

25

30

35

Imp

rovem

en

t (%

)

Vaccum spacer – scaling effect

Benefits increase with scaling

SAC with Nitride Spacer

SAC with Air Spacer

2-10-2010-24-

Outline

• Introduction

• MOSFETs with Vacuum-Spacer

• Vacuum-Corridor Interconnects ▪

The Proposed Process of Air-Corridor ▪

The Characteristics of Air-Corridor

• Future Works

2-10-2010-25-

Previous Air-Gap Structures

An air gap is located only between metals

2-10-2010-26-

Proposed Vacuum-Corridor structures

Etch Stop layer

Metal

Dielectric Beam

Mutual Capacitance : CM

Total Capacitance : CTOTAL

Overlap Capacitance : CO

CM

CO

CO

CM

CTOTAL ∝

Delay, CM ∝

Crosstalk Noise

2-10-2010-27-

Process Flow I

Sacrificial Material MetalIMDStopper

(a) Via Etch (b) Line Etch (c) Metal depo & CMP

(d) Etch Stopper & IMD (e) Dielectric beam Spacer Formation

(f) Sacrificial material depo & CMP

Jemin Park et. al., VMIC, Fremont CA, Oct. 2008, p229-234

2-10-2010-28-

Jemin Park et. al., VMIC, Fremont CA, Oct. 2008, p229-234

Process Procedure II

(g) Metal 2 Process (h) Metal 3 process (i) Removal all Sacrificial Material

Sacrificial Material MetalIMDStopper

2-10-2010-29-

Metal Width 59nm 40nm 28nm 20nm

Metal Space 59nm 40nm 28nm 20nm

Metal A/R 1.8 1.8 1.9 2.0

Metal Thick 1062Å 720Å 532Å 400Å

Required Bulk Dielectric Constant 2.9 2.7 2.5 2.3

Stopper Layer Thick 10nm 10nm 5nm 5nm

IMD Thick (Metal + Via Height) 2124Å 1440Å 1064Å 800Å

Beam Dielectric Constant for Air-Corridor 2.9 2.9 2.9 2.9

Assumption for simulation2007 ITRS spec

ITRS Key Parameters of Each Generation

2-10-2010-30-

0

200

400

600

800

1000

20 30 40 50 60 70 80Air percentage (%)

Cap

acitan

ce (

aF/u

m)

20% of vacuum percentage

80% of vacuum percentageThicker Beam Dielectric

Total Capacitance

Mutual Capacitance

CTOTAL,con

CMutual,con

Dielectric Beam

Metal Line

Capacitances vs. Vacuum Percentage

2-10-2010-31-

Insensitive to via height

0

200

400

600

800

1000

1200

1400

360 576 792 1008 1224 1440

Via Height (A)

Tot

al C

apac

itan

ce (

aF/u

m)

0

100

200

300

400

500

360 576 792 1008 1224 1440Via Height (A)

Mutu

al C

apac

itan

ce (

aF/u

m)

Conventional Structure

Air-Corridor Structure

Conventional Structure

Air-Corridor Structure

2-10-2010-32-

0

1

2

3

4

5

360 576 792 1008 1224 1440Metal Height (A)

Rel

ativ

e RC d

elay

48

51

54

57

60

Impro

vem

ent

(%)

Vacuum-Corridor has less RC delay and higher CMP margin

Relative Delay vs. Metal Height

Conventional Structure

Air-Corridor Structure

2-10-2010-33-

The Effective k of Vacuum-Corridor Interconnects

No Solution

Bea

m D

iele

ctric

Const

ant

20 30 40 50 60 70 80

Air Percentage (%)

2.25

2.9

3.3

3.6

3.9

1.31.4

1.51.6

1.71.8

1.92.0

2.12.22.3

2.42.5

2.6No Solution

2-10-2010-34-

Papers and Patents

PAPERS:

1. “An Vacuum-Sheath Interconnect Structure for Dense Memory” Je Min Park and Chenming HuElectronics Letters, accepted and will be published on December, 20092. “Air-Spacer MOSFET with Self-Aligned Contact for Future Dense Memories”Je Min Park and Chenming HuElectron Device Letters, accepted and will be published on December, 20093. “Gate Last MOSFET with Air Spacer and Self-Aligned Contacts for Dense Memories”Je Min Park and Chenming HuVLSI-TSA, pp105-106, Taiwan, Apr. 20094. “Air-Spacer MOSFET Technology for 20nm Node and Beyond” Je Min Park and Chenming HuICSICT, pp53-56, China, Oct. 20085. “Air-Spacer Self-Aligned Contact MOSFET for Future Dense Memories” Je Min Park and Chenming HuSISPAD, pp313-316, Japan, Sep. 20086. “An-Air-Corridor Interconnect Structure”Je Min Park and Chenming HuVMIC, pp229-234, Fremont, CA., Oct. 2008

PATENTS: (UC Patents Pending)

1. “Transistor Speed And Power Improvements” Je Min Park and Chenming HuUC Case 2008-107-02. "Air Corridor Interconnect Structure" Je Min Park and Chenming HuUC Case 2009-044-0