Post on 28-Feb-2017
IEEE—ICET 2006 2nd International Conference on Emerging Technologies Peshawar, Pakistan 13-14 November 2006
1-4244-0502-5/06/$20.00©2006 IEEE 205
Single Chip FPGA Based Realization of Arbitrary
Waveform Generator using Rademacher and
Walsh Functions
Syed Manzoor Qasim and Shuja Ahmad Abbasi
Department of Electrical Engineering, VLSI Research Lab King Saud University, Riyadh, Saudi Arabia 11421
{smanzoor, abbasi}@ksu.edu.s
Abstract: Arbitrary waveform generators (AWGs) are
becoming increasingly important for test and
measurement applications. This paper describes a
new approach for generating arbitrary waveforms using FPGA and a set of Rademacher and Walsh
Functions. Utilizing these orthogonal functions, any
periodic waveform can be realized. Recent advancements in Field Programmable Gate Array
(FPGA) technology have made waveform generation
very easy and cost-effective. For demonstration
purpose we used a custom defined arbitrary
waveform that is a concatenation of trapezoidal,
sinusoidal and triangular waveforms. Simulation
results for the proposed AWG are presented. Top-
down approach has been adopted to realize the
waveform generator in Spartan-3 FPGA. The
maximum clock frequency for this design is 24.944
MHz with a power consumption of 62 mW.
Keywords: Arbitrary Waveform Generation, Field-
Programmable Gate Array (FPGA), Rademacher,
Walsh Functions, VHDL
1. INTRODUCTION
The ability to generate arbitrary waveform is
of importance for many commercial and military
applications. By using arbitrary waveforms,
engineers and scientists are able to generate
unique waveform signals that are specific to
their applications. Most often, arbitrary
waveforms are designed to simulate real world
signals. A number of techniques utilizing both
analog and digital approaches are available for
the generation of arbitrary waveforms. However,
digital methods, based on high-level design
methodology offer better flexibility at the cost of
increased complexity.
Orthogonal functions such as Rademacher and Walsh functions are a set of discrete valued functions [1] [5]. These functions and their transforms are important analytical tools for
signal processing and have wide applications in digital communication, digital image processing, statistical analysis and waveform generation [3].
Since Walsh functions are binary related, they are easy to generate and control using relatively simple hardware and readily lend itself for real-time waveform generation ideal for the synthesis of different waveforms.
With the recent advancement in Field Programmable Gate Array (FPGA) technology, it is now possible to realize high performance Arbitrary Waveform Generator (AWG) in a single chip. This will drastically reduce the system cost and thus avoid the dependency on external function generators to generate arbitrary waveforms. These waveforms can be easily generated on-chip. Being dynamically recon-figurable, the same FPGA can be used for different applications [6].
The objective of this paper is to realize a single-chip low cost approach for arbitrary waveform generation. To achieve this we used FPGA architecture for high-speed generation of arbitrary waveforms. In this paper, we have used a set of Rademacher and Walsh functions for the generation of digital arbitrary waveform in FPGA.
The rest of the paper is organized as follows. Orthogonal functions such as Rademacher and Walsh functions are defined and the methods used for their generation are discussed in section 2. Section 3 gives a brief overview of the Spartan-3 FPGA architecture and the top-down design methodology adopted in this work is described in section 4. In section 5, techniques for the generation of arbitrary waveform using Rademacher-Walsh functions is described. Section 6 summarizes the FPGA implementation results and finally section 7 gives some concluding remarks.
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2. GENERATION OF RADEMACHER
AND WALSH FUNCTIONS
The Rademacher functions constitute an
incomplete and orthogonal set of periodic square
waveforms of amplitude +1 and 1.
Mathematically, kth order Rademacher function
is defined by the relation [4]
(k+1, x) = sgn {sin (2 2k x)}, k =
0,1,2,.... (1)
where (0, x) = 1 and
0,1
0,1sgn
x
xx (2)
Fig. 1 depicts the first four Rademacher
functions.
Fig. 1. First four Rademacher Functions
The Rademacher functions are generated as
follows [4]:
Let (0, x) be the function with the
value 1 for the entire interval of duration
T = 1 i.e., (0, x) = 1.
To obtain (1, x), divide the interval
(0,1) in half, and let the value of (1, x)
in the first half interval be +1 and in the
second half of the interval 1.
To obtain (2, x), divide each of the
intervals (0,1/2) and (1/2,1) in half and
let the value of the function in the first
half of each interval be +1 and in the
second half of the interval 1.
The process is repeated until each interval is a single-pulse element.
The same functions generated using
MATLAB for the purpose of verification are
shown in Fig.2.
Fig. 2. First four Rademacher functions generated using
MATLAB
A simple digital counter circuit is used for the
generation of Rademacher functions.
The Walsh functions form a complete and orthogonal set of functions of rectangular waveforms taking only two amplitudes +1 and
1. We denote the Walsh function by xn,
defined on the interval [0,1) such that [5]
10,1x0, x (3)
and
1,0,,10
i
nN
i
nxin,x i (4)
where the integer n is represented by [5]
N
i
i
i nn0
2 (5)
Fig. 3 shows the first eight continuous Walsh
functions. All the eight functions take on the
values {+1, 1}. Every function starts with the
value +1.
The same functions generated using
MATLAB for verification purpose are shown in
Fig.4. The Walsh functions can be generated by
many methods [4]. One way to compute the
Walsh functions are by using Rademacher
functions. The Walsh functions are generated
using products of the Rademacher functions.
The Walsh functions are developed as products
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x0
1( 0 , x )
x
( 1 , x )
0
1
- 1
1
1½
x
( 2 , x )
1½
x
( 3 , x )
1½
x
( 4 , x )
1½
x1½
( 6 , x )
x1½
x1½
1
- 1
1
- 1
1
- 1
1
- 1
1
- 1
1
- 1
0
0
0
0
0
0
( 7 , x )
( 5 , x )
Fig. 3. First eight continuous Walsh functions
Fig. 4. MATLAB generated First Eight Walsh functions
of the Rademacher functions, based on the gray
code conversion of the Walsh function index
sequence. If we convert the ±1 amplitudes of the
Walsh functions to a binary logic {0,1}
representation with the conversions +1 “0”
and 1 “1”, then multiplication of
Rademacher functions is equivalent to
Exclusive-OR operation.
3. SPARTAN-3 FPGA
ARCHITECTURE
The Spartan-3 FPGA architecture consists of
an array of Configurable Logic Blocks (CLBs),
which are the basic elements that can be
programmed to perform various logic functions.
Each CLB is coupled with a programmable
interconnect switch matrix that connects the
CLB to adjacent and nearby CLBs [6].
Each CLB contains four logic slices, where
each logic slice usually consists of two four-
input Look Up Tables (LUTs), two configurable
flip-flops, some muxes, and other control logic.
In addition to the CLBs and the switch matrices,
the Spartan-3 FPGA have a number of higher–
level logic blocks such as block RAMs
(BRAMs), 18-bit multipliers, digital clock
managers (DCMs) and even CPUs [6].
4. DESIGN FLOW
An FPGA design flow is the process of
turning an FPGA design into a correctly timed
bitstream file used to program the FPGA. In
order to realize any algorithm on an FPGA it
must be programmed (configured) first. To
achieve this, a design methodology is adopted.
Usually, design entry is done using hardware
description language (HDL) such as Very High
Speed Integrated Circuit Hardware Description
Language (VHDL) or Verilog. In this paper, the
design entry is done in VHDL.
The objective is to make the system
description independent of the physical
hardware such that it can be used on other
FPGAs and even on Application Specific
Integrated Circuits (ASICs). Once a design has
been completed it is simulated to verify the
correct operation. A netlist is generated from the
design and is mapped onto the FPGA using
synthesis, place and route and optimizing tools.
Mapping produces a bit-stream file that is used
to program the FPGA [7].
5. GENERATION OF ARBITRARY
WAVEFORM USING WALSH
FUNCTIONS
Generating arbitrary waveforms using Walsh
functions consists of three stages:
1) Generation of the Rademacher functions
2) Generation of the Walsh functions using
Rademacher functions, and
3) Adjustment of the coefficients of each
Walsh function.
Generation of periodic arbitrary waveform
involves weighted addition of different Walsh
functions. The addition of more Walsh functions
would produce a smoother approximation of a
particular waveform, of course at the cost of
more computational complexity. The
functionality of the arbitrary waveform
generator is written in VHDL and synthesized
into a configuration file that is downloaded into
the Spartan-3 FPGA [6]. This is done using
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Xilinx ISE 7.1i software. By using a single,
appropriately sized FPGA, digital arbitrary
waveform as defined by xf can be
synthesized thus avoiding the use of any analog
to digital converter and hence minimizing the
area and cost of hardware.
Since Walsh functions constitute a complete
set, any arbitrary function xf can be
expressed as follows [2]:
0
,n
n xnAxf
(6)
where, nA are the coefficients of the expansion
and can be obtained by [2]
1
0
, dxxnxfAn
(7)
The arbitrary waveform defined by (8) is shown
in fig. 5.
xf =
18125.0267.4267.4
8125.0625.0267.4667.2
625.0375.0)375.0(4sin(
375.025.08.18.4
25.0125.06.0
125.008.4
xx
xx
xx
xx
x
xx
(8)
The sixty four expansion coefficients required for the generation of arbitrary waveform as defined by (8) are listed in Table 1. Some of the coefficients turn out to be zero.
As shown in Table 1, approximations to the arbitrary waveform can be obtained by using 64 Walsh functions.
Fig. 5. Custom-defined arbitrary waveform
For validation of results, MATLAB was
used. Fairly smooth arbitrary waveform was
obtained through MATLAB simulation as
shown in Fig. 6.
TABLE 1WALSH FUNCTION COEFFICIENTS
Walsh coefficients (n = 64)
A0 0.4591 A23 -0.0669 A46 -0.0023
A1 0 A24 -0.0214 A47 -0.0040
A2 -0.0083 A25 0.0084 A48 -0.0024
A3 -0.0008 A26 0.0083 A49 0
A4 0.0166 A27 0.0048 A50 0
A5 -0.1758 A28 -0.0084 A51 0.0031
A6 0.0008 A29 0.0214 A52 0
A7 0.0085 A30 -0.0048 A53 0.0028
A8 0 A31 -0.0081 A54 -0.0031
A9 -0.0658 A32 -0.0006 A55 0
A10 -0.0048 A33 -0.0159 A56 0
A11 -0.0043 A34 -0.0022 A57 0.0013
A12 0.0658 A35 -0.0009 A58 0.0012
A13 0 A36 0.0159 A59 0
A14 -0.0040 A37 0 A60 -0.0013
A15 -0.1369 A38 -0.0012 A61 0
A16 -0.0006 A39 -0.0333 A62 0
A17 -0.0318 A40 -0.0107 A63 0.0009
A18 -0.0039 A41 0.0043
A19 -0.0019 A42 0.0042
A20 0.0318 A43 0.0023
A21 0 A44 -0.0043
A22 -0.0022 A45 0.0107
Fig. 6. MATLAB generated arbitrary waveform
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6. FPGA IMPLEMENTATION
RESULTS
Based on the given architecture, design and simulation of the AWG has been performed using VHDL. The design is synthesized and placed and routed into Xilinx Spartan-3 FPGA (XC3S200-4ft256) using Xilinx ISE 7.1i [8]. The hardware resource utilization is reported for an XC3S200-4ft256 Spartan-3 FPGA device and the results are summarized in Table 2.
Modelsim is used for both pre-synthesis and post-synthesis simulation. Fig. 7 represents the snapshot of simulation results of Rademacher
functions (R1 R6), Walsh functions (W1 W63)and 16-bit digital arbitrary waveforms (P0 P15).As shown in fig. 7, clk is the clock signal, reset is the reset signal. The estimated power consumption of the architecture was obtained with Xilinx XPower software using a clock frequency of 24.944 MHz.
7. CONCLUSION A new technique for high-speed arbitrary waveform generation using FPGA and a set of Rademacher and Walsh functions has been presented. Rademacher and Walsh are
Fig. 7. Snapshot of Simulation of Rademacher, Walsh and arbitrary waveform.
210
orthogonal functions widely used in engineering applications such as waveform generation. Xilinx spartan-3 (XC3S200-4FT) FPGA chip is used. FPGA implementation results have been presented which shows that the proposed design is very compact utilizing just 17% of total FPGA slices, so there is a possibility of implementing more parallel processors on the same FPGA.
TABLE 2HARDWARE RESOURCE UTILIZATION FOR XC3S200 SPARTAN-3
FPGA
Number of Slices
340 out of 1,920 17%
Number 4 input LUTs 540 out of 3,840 14%
Number of bonded IOBs 87 out of 173 50%
Number of GCLKs 1 out of 8 12%
Maximum Frequency (After Place and Route) : 24.944
MHz
Total estimated power consumption : 62 mW
The proposed design being digital can be easily integrated as an IP Core for on-chip waveform generation. AWG works correctly as shown by the simulation results and validated by MATLAB.
The chip was thoroughly tested after implementation. The maximum clock frequency obtained after place and route of the design is 24.944 MHz consuming only 62 mW of power.
REFERENCES
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