GPS Locking the IC 910-H

By RexMoncur

VK7MO

BLOCK DIAGRAM

GPSDO

PLL & 30.2

MHz Osc

IC 910-H

10

MHz

30.2

MHz

External Oscillator Input

Circuit Mods to IC 910-H

Internal Mods to IC 910-H

30.2 MHz Oscillator and PLL

PLL Block Diagram

PLL Construction

Stability at 1296 MHz

1 Hz

Receiver &

SigGen

locked to

separate

GPSs

Receiver &

SigGen

locked to

same GPS

50 mHz

Phase Noise v Loop Time Constant

Tc= 20 micro-seconds

Phase Noise at 5 Hz = -55 dBc/Hz

1296 MHz: Yellow = PLL with cheap Hi-Q Oscillator, Blue = HP SigGen

Tc= 3000 micro-seconds

Phase Noise at 5 Hz = -45 dBc/Hz

Phase Noise with Oven Oscillator

1296 MHz: Yellow = Oven Oscillator, Blue = HP SigGen

Phase Noise for both at 5 Hz = -70 dBc/Hz

10 Hz off

10 Hz off

5 Hz Phase Noise at 1296 MHz

•161 PLL with Hi-Q Osc -55 dBc/Hz

•RigLockwith Hi-Q Osc -58 dBc/Hz

•161 PLL with Oven Osc -70 dBc/Hz

•HP SigGen -70 dBc/Hz

•10 GHz DB6NT Trans. -34 dBc/Hz

CONCLUSIONS

•Need a good quality oscillator to get

lowest phase noise.

•Hum can be a problem –mount in

shielded box and bypass liberally with

electrolytics.

•Stability is better than 0.1 Hz at 1296 MHz

and more than adequate for JT65a.

•Accuracy is better than 1 Hz at 1296 MHz