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EE466: VLSIDesign
Lecture 8: Combinational Circuits
8: Combinational Circuits Slide 2CMOS VLSI Design
Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio
8: Combinational Circuits Slide 3CMOS VLSI Design
Example 1MULTIPLEXER
1) Sketch a design using AND, OR, and NOT gates.
8: Combinational Circuits Slide 4CMOS VLSI Design
Example 1MULTIPLEXER
1) Sketch a design using AND, OR, and NOT gates.
D0S
D1S
Y
8: Combinational Circuits Slide 5CMOS VLSI Design
Example 22) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
8: Combinational Circuits Slide 6CMOS VLSI Design
Example 22) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
Y
D0S
D1S
8: Combinational Circuits Slide 7CMOS VLSI Design
Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y Y
Y
D
Y
(a) (b)
(c) (d)
8: Combinational Circuits Slide 8CMOS VLSI Design
Example 33) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
8: Combinational Circuits Slide 9CMOS VLSI Design
Example 33) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
Y
D0SD1S
8: Combinational Circuits Slide 10CMOS VLSI Design
Compound Gates Logical Effort of compound gates
ABCD
Y
ABC Y
A
BC
C
A B
A
B
C
D
A
C
B
D
2
21
4
44
2
2 2
2
4
4 4
4
gA = 6/3
gB = 6/3
gC = 5/3
p = 7/3
gA =
gB =
gC =
p =
gD =
YA
A Y
gA = 3/3
p = 3/3
2
1YY
unit inverter AOI21 AOI22
A
C
DE
Y
B
Y
B C
A
D
E
A
B
C
D E
gA =
gB =
gC =
gD =
2
2 2
22
6
6
6 6
3
p =
gE =
Complex AOI
Y A B C Y A B C D Y A B C D E Y A
8: Combinational Circuits Slide 11CMOS VLSI Design
Compound Gates Logical Effort of compound gates
ABCD
Y
ABC Y
A
BC
C
A B
A
B
C
D
A
C
B
D
2
21
4
44
2
2 2
2
4
4 4
4
gA = 6/3
gB = 6/3
gC = 5/3
p = 7/3
gA = 6/3
gB = 6/3
gC = 6/3
p = 12/3
gD = 6/3
YA
A Y
gA = 3/3
p = 3/3
2
1YY
unit inverter AOI21 AOI22
A
C
DE
Y
B
Y
B C
A
D
E
A
B
C
D E
gA = 5/3
gB = 8/3
gC = 8/3
gD = 8/3
2
2 2
22
6
6
6 6
3
p = 16/3
gE = 8/3
Complex AOI
Y A B C Y A B C D Y A B C D E Y A
8: Combinational Circuits Slide 12CMOS VLSI Design
Example 4 The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.
8: Combinational Circuits Slide 13CMOS VLSI Design
Example 4 The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.
Y
D0S
D1S
Y
D0SD1S
H = 160 / 16 = 10B = 1N = 2
8: Combinational Circuits Slide 14CMOS VLSI Design
NAND Solution
Y
D0S
D1S
8: Combinational Circuits Slide 15CMOS VLSI Design
NAND Solution
Y
D0S
D1S
2 2 4
(4 / 3) (4 / 3) 16 / 9
160 / 9
ˆ 4.2
ˆ 12.4
N
P
G
F GBH
f F
D Nf P
8: Combinational Circuits Slide 16CMOS VLSI Design
Compound Solution
Y
D0SD1S
8: Combinational Circuits Slide 17CMOS VLSI Design
Compound Solution
4 1 5
(6 / 3) (1) 2
20
ˆ 4.5
ˆ 14
N
P
G
F GBH
f F
D Nf P
Y
D0SD1S
8: Combinational Circuits Slide 18CMOS VLSI Design
Example 5 Annotate your designs with transistor sizes that
achieve this delay.
YY
8: Combinational Circuits Slide 19CMOS VLSI Design
Example 5 Annotate your designs with transistor sizes that
achieve this delay.
6
6 6
6
10
10Y
24
12
10
10
8
8
88
8
8
88
25
25
2525Y
16 16160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36
8: Combinational Circuits Slide 20CMOS VLSI Design
Input Order Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling• If A arrives latest?• If B arrives latest?
6C
2C2
2
22
B
Ax
Y
8: Combinational Circuits Slide 21CMOS VLSI Design
Input Order Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling• If A arrives latest? 2• If B arrives latest? 2.33
6C
2C2
2
22
B
Ax
Y
8: Combinational Circuits Slide 22CMOS VLSI Design
Inner & Outer Inputs Outer input is closest to rail (B) Inner input is closest to output (A)
If input arrival time is known– Connect latest input to inner terminal
2
2
22
B
A
Y
8: Combinational Circuits Slide 23CMOS VLSI Design
Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)– Boost size of noncritical input– So total resistance is same
gA =
gB =
gtotal = gA + gB =
Asymmetric gate approaches g = 1 on critical input But total logical effort goes up
Areset
Y
4/3
2
reset
A
Y
8: Combinational Circuits Slide 24CMOS VLSI Design
Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)– Boost size of noncritical input– So total resistance is same
gA = 10/9
gB = 2
gtotal = gA + gB = 28/9
Asymmetric gate approaches g = 1 on critical input But total logical effort goes up
Areset
Y
4
4/3
22
reset
A
Y
8: Combinational Circuits Slide 25CMOS VLSI Design
Symmetric Gates Inputs can be made perfectly symmetric
A
B
Y2
1
1
2
1
1
8: Combinational Circuits Slide 26CMOS VLSI Design
Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.
– gu =
– gd =
1/2
2A Y
1
2A Y
1/2
1A Y
HI-skewinverter
unskewed inverter(equal rise resistance)
unskewed inverter(equal fall resistance)
8: Combinational Circuits Slide 27CMOS VLSI Design
Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
1/2
2A Y
1
2A Y
1/2
1A Y
HI-skewinverter
unskewed inverter(equal rise resistance)
unskewed inverter(equal fall resistance)
8: Combinational Circuits Slide 28CMOS VLSI Design
HI- and LO-Skew Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.
Skewed gates reduce size of noncritical transistors– HI-skew gates favor rising output (small nMOS)– LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction But larger for the other direction
8: Combinational Circuits Slide 29CMOS VLSI Design
Catalog of Skewed Gates
1/2
2A Y
Inverter
B
AY
B
A
NAND2 NOR2
HI-skew
LO-skew1
1A Y
B
AY
B
A
gu = 5/6gd = 5/3gavg = 5/4
gu = 4/3gd = 2/3gavg = 1
gu =gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
Y
Y
1
2A Y
2
2
22
B
AY
B
A
11
4
4
unskewedgu = 1gd = 1gavg = 1
gu = 4/3gd = 4/3gavg = 4/3
gu = 5/3gd = 5/3gavg = 5/3
Y
8: Combinational Circuits Slide 30CMOS VLSI Design
Catalog of Skewed Gates
1/2
2A Y
Inverter
1
1
22
B
AY
B
A
NAND2 NOR2
1/21/2
4
4
HI-skew
LO-skew1
1A Y
2
2
11
B
AY
B
A
11
2
2
gu = 5/6gd = 5/3gavg = 5/4
gu = 4/3gd = 2/3gavg = 1
gu =gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
Y
Y
1
2A Y
2
2
22
B
AY
B
A
11
4
4
unskewedgu = 1gd = 1gavg = 1
gu = 4/3gd = 4/3gavg = 4/3
gu = 5/3gd = 5/3gavg = 5/3
Y
8: Combinational Circuits Slide 31CMOS VLSI Design
Catalog of Skewed Gates
1/2
2A Y
Inverter
1
1
22
B
AY
B
A
NAND2 NOR2
1/21/2
4
4
HI-skew
LO-skew1
1A Y
2
2
11
B
AY
B
A
11
2
2
gu = 5/6gd = 5/3gavg = 5/4
gu = 4/3gd = 2/3gavg = 1
gu = 1gd = 2gavg = 3/2
gu = 2gd = 1gavg = 3/2
gu = 3/2gd = 3gavg = 9/4
gu = 2gd = 1gavg = 3/2
Y
Y
1
2A Y
2
2
22
B
AY
B
A
11
4
4
unskewedgu = 1gd = 1gavg = 1
gu = 4/3gd = 4/3gavg = 4/3
gu = 5/3gd = 5/3gavg = 5/3
Y
8: Combinational Circuits Slide 32CMOS VLSI Design
Asymmetric Skew Combine asymmetric and skewed gates
– Downsize noncritical transistor on unimportant input
– Reduces parasitic delay for critical input
Areset
Y
4
4/3
21
reset
A
Y
8: Combinational Circuits Slide 33CMOS VLSI Design
Best P/N Ratio We have selected P/N ratio for unit rise and fall
resistance ( = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter
– Delay driving identical inverter
– tpdf =
– tpdr =
– tpd =
– Differentiate tpd w.r.t. P
– Least delay for P =
1
PA
8: Combinational Circuits Slide 34CMOS VLSI Design
Best P/N Ratio We have selected P/N ratio for unit rise and fall
resistance ( = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter
– Delay driving identical inverter
– tpdf = (P+1)
– tpdr = (P+1)(/P)
– tpd = (P+1)(1+/P)/2 = (P + 1 + + /P)/2
– Differentiate tpd w.r.t. P
– Least delay for P =
1
PA
8: Combinational Circuits Slide 35CMOS VLSI Design
P/N Ratios In general, best P/N ratio is sqrt of equal delay ratio.
– Only improves average delay slightly for inverters– But significantly decreases area and power
Inverter NAND2 NOR2
1
1.414A Y
2
2
22
B
AY
B
A
11
2
2
fastestP/N ratio gu =
gd =gavg =
gu =gd =gavg =
gu =gd =gavg =
Y
8: Combinational Circuits Slide 36CMOS VLSI Design
P/N Ratios In general, best P/N ratio is sqrt of that giving equal
delay.– Only improves average delay slightly for inverters– But significantly decreases area and power
Inverter NAND2 NOR2
1
1.414A Y
2
2
22
B
AY
B
A
11
2
2
fastestP/N ratio gu = 1.15
gd = 0.81gavg = 0.98
gu = 4/3gd = 4/3gavg = 4/3
gu = 2gd = 1gavg = 3/2
Y
8: Combinational Circuits Slide 37CMOS VLSI Design
Observations For speed:
– NAND vs. NOR– Many simple stages vs. fewer high fan-in stages– Latest-arriving input
For area and power:– Many simple stages vs. fewer high fan-in stages