Post on 15-Jan-2016
description
COTS Based High Performance Radar and EW Development Platform
HPEC September 2011Mikael Taveniku, XCube
Gunnar Hillerstrom, Swedish Defence Research Agency
04/21/23 Page 1XCube 2011
COTS EW/Radar Development Platform
04/21/23XCube 2011 Page 2
Adarate FPGA Front end & analog interface (ADC/DAC)
NVIDIAFloating point DSP & HMI- GPGPU GTX590
Adapteva (future)Complex CPU/DSPintensive processing- ATDSP (future) / Others
Data Storage and ControlXCube Development Platform- Control / Record / Replay Software- Dual Xeon CPU- Up to 144GByte Memory- >4.4GByte/s Throughput- >8 GByte/s Burst- 96TB removable storage (shown)
- Virtex6 130LXT – 475SXT- 2x National ADC083000 (selectable)- 2x Analog devices AD9739- 2x 1Gbit Ethernet - PCI-express
Other
Demo Setup (LPI Radar Simulation & Detection)
04/21/23 XCube Page 3
Signal Generator
ReceiverADC
FPGAFrontend
StreamBuffers
Disk Scheduler
Disk Manager
Control PC
PCIe
GP-GPU
TransmitDAC
HRFT Standalone
HRFT Internaldisk
Processor Array (future FMC) disk
Diskwriter
Tight Timing High Throughput
Diskwriter
DMA
Decoupling
Buffering and ProcessingExternal Interfaces
Host Processing2.4Gsps - 8 bit data8 Channels 150MHz (I/Q-data)Window FFT waterfall1200MByte/s throughput (and storage)
Radar (FMCW) / Frequency Hop (FH)
InterfaceManager