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COMS 361Computer Organization

Title: InstructionsDate: 9/21/2004Lecture Number: 8

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Announcements

• Homework 3– Due 9/28/04

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Review

• Instructions– MIPS arithmetic instruction format– Immediate instructions– MIPS load and store instructions– Addressing

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Outline

• Instructions– MIPS load and store instruction format– MIPS immediate instruction format– Addressing– MIPS branch instructions and format

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Immediate Instructions• Frequently constants are added during

program execution– Increment (i++)– Speed execution if these constants could be in the

instruction instead of in memory• MIPS provides an immediate version of some

instructions, which contain a constant– C/C++ code i = i + 1;– MIPS code addi $s0, $s1, 1

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Immediate Instructions• Syntax is similar to R-type instructions

– Except a number needs to be stored in the instruction

– Where should the immediate value be put using this instruction format?

– Hummmmm

op rs rt rd shamt funct

6 5 5 5 5 6

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Data Transfer Instructions

C/C++ code: b = A[8];MIPS code: lw $t0, 32($s2)

• Data transfer instruction syntax– 1 2, 3(4)1) Operation (instruction) name2) Destination register3) Numerical offset in bytes4) Register containing the base address of the array

register contains a pointer to memory

Base register

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Data Transfer Instructions

lw $t0, 32($s2)

– 16-bit address means words within a 215 range around the address in the base register can be loaded

• Positive and negative offsets– 16-bit immediate number is the same number of

bits as a signed short integer in C/C++

op rs rt Address or immediate value

6 6 5 16

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Design Principle 3

• Good design demands good comprises

• MIPS comprise– Keep all instructions the same size (32-bits)– Allow different instruction formats for different

types of instructions

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Machine language

• Example: lw $t0, 32($s2)

• The effective address (EA) of the word to load is computed as:– Address stored in the $s2 register (the base

address) plus the offset amount– Addressing mode is called

• register indirect with immediate offset

35 18 9 32op rs rt number

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Machine language

–register indirect with immediate offset

–EA = register + signed immediate

• There are other address schemes used by other architectures, but only this one for MIPS

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Pitfall

• Forgetting sequential word address in a byte addressable machine differ by the word size (in bytes), not 1

• MIPS is a word aligned machine– Word addresses must be a multiple of 4– A 32-bit word actually occupies four contiguous

locations (bytes) of main memory

0 1 2 3 4 5 6 7 8 9 10 11 12 13 wordaddress

8-bit data

word 1 word 2 word 3

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Pitfall

0 1 2 3Aligned

NotAligned

Bytes in Word

Word Location

– 0, 4, 8 and 12 are valid word addresses.– 1, 2, 3, 5, 6, 7, 9, 10 and 11 are not valid word

addresses.– Unaligned memory accesses result in a bus error,

which you may have unfortunately seen before

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Stored Program Concept

• Fetch & Execute Cycle– Instructions are fetched (from memory) and put

into a special register– Bits in the register "control" the subsequent

actions– Fetch the “next” instruction and continue

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Fetch and Execute Cycle

How is the address of the next instruction determined?

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Fetch and Execute Cycle

• Sometimes the address of the next instruction to execute is the next word address

• Other times it is not• What kind of C++ statement would cause non-

sequential instruction execution?if (condition) {

blah;

blah;

}

more blah;

if the condition is not trueexecution jumps to the more blah instructionout of sequence instruction execution

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Control Flow

• Decision making instructions– Alter the control flow

• Change the "next" instruction to be executed– MIPS conditional branch instructions

•beq $t0, $t1, EQ– branch if equal– If the contents of register $t0 == $t1 the next instruction to be

executed is the one associated with the label EQ •beq $t0, $t1, NEQ

– branch if NOT equal– Execute instruction associated with NEQ if the contents of

register $t0 != $t1

A label you create or make up

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Control Flow

– Example: conditional branch instructions• C/C++ code: if(i == j) {h = i + j;}

• MIPS code: bne $s0, $s1, NEQadd $s3, $s0, $s1 NEQ: ....

• Notice: in MIPS we reversed the condition to goto NEQ– If the condition is NOT true, skip the next instruction– If the condition is true, execute the next instruction and continue

sequential instruction execution

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Conditional Branch Instructions

• The conditional branch instructions require• 1 2, 3, 4

– 1 is the op code for the instruction– 2 is the first operand (register address)– 3 is the second operand (register address)– 4 is the target address

• Actually it is an offset amount from the current instruction

• Can be positive or negative– Branch later in the code– Branch earlier in the code (previous statements)

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Conditional Branch Instructions

• Sounds like conditional branch instructions can utilize the:– I-type format

5 17 18 25op rs rt number

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Conditional Branch Instructions

– C++ code: if (i == j) {f = g + h;

} else {f = g – h;

}

– MIPS code: bne $s3, $s4, Elseadd $s0, $s1, $s2

Else: sub $s0, $s1, $s2

– But of course there is a problem here• The instruction with the Else label is executed

regardless of the condition value– Need to unconditionally branch to a label

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Control Flow

• MIPS also provides an unconditional branch instruction:– j label

• Introduce a new type of instruction format– j-type for branch instructions

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Control Flow– C++ code: if (i == j) { f = g + h; }

else { f = g – h; }

– MIPS code: bne $s3, $s4, Elseadd $s0, $s1, $s2j Endif

Else: sub $s0, $s1, $s2Endif:blah

beq $s4, $s5, EQsub $s3, $s4, $s5j Endif

EQ: add $s3,$s4,$s5Endif:blah

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Control Flow

• Unconditional branch instruction requires only an op code and an address to jump to

Op code Address

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Control

• Can you build a simple for loop in MIPS assembly language?

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Summary so far

• Instruction Meaning– add $s1,$s2,$s3 $s1 = $s2 + $s3– sub $s1,$s2,$s3 $s1 = $s2 – $s3– lw $s1,100($s2) $s1=Memory[$s2+100] – sw $s1,100($s2) Memory[$s2+100]=$s1– bne $s4,$s5,L Next instr. is at L if $s4 !=

$s5– beq $s4,$s5,L Next instr. is at Label if $s4 ==

$s5– j Label Next instr. is at Label

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Summary so far

• Instruction formats

R op rs rt rd shamt funct

I op rs rt 16 bit address

J op 26 bit address