Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-1

Chapter 5 MOS Capacitors

MOS: Metal-Oxide-Semiconductor

SiO2

metal

gate

Si body

Vg

gate

P-body

N+

MOS capacitor MOS transistor

Vg

SiO2

N+

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-2

How does one arrive at this energy-band diagram for Vg = 0?

N+ po

lys i

l icon

SiO

2

(a)

Ec

Ev

Ec

Ev

Ec

Ev

Ef

3.1

e V

9eV

3.1

eV

(b)

P-Si

licon

body

gate body

Chapter 5 MOS Capacitors

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-3

5.1 Flat-band Condition and Flat-band Voltage

E0 : Vacuum levelE0 – Ef : Work functionE0 – Ec : Electron affinitySi/SiO2 energy barrier

sgfbV ψψ −=

χSiO2=0.95 eV

9 eV

Ec, Ef

Ev

Ec

Ev

Ef

3.1 eV q ψs= χSi + (Ec–Ef) qψg χSi

E0

3.1 eV

Vfb

N+ -poly-Si P-body

4.8 eV

=4.05eV

Ec

Ev

SiO2

The band is flat at a particular gate voltage.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-4

5.2 Surface Accumulation

oxsfbg VVV ++= φ

sφ is negligible when

3.1eV

Ec ,Ef

Ev E0

Ec

EfEv

M O S

qVg

Vox

qφs

Make Vg < Vfb .

the surface is in accumulation because a little band-bending leads to a large accumulation charge.

φs : surface potential, band bendingVox: voltage across the oxide

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-5

5.2 Surface Accumulation

fbgox VVV −=

)( fbgoxacc VVCQ −−=

oxsox CQV /−=

oxaccox CQV /−=Gauss Law

SiO2

gate

P-Si body

- - - - - - -

+ V

Vg < Vf b

+ + + + + + accumulation charge, Qacc

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-6

5.3 Surface Depletion

ox

ssa

ox

depa

ox

dep

ox

sox C

qNC

WqNCQ

CQV

φε2==−=−=

SiO2

gate

P-Si body

+ + + + + +- - - - - - -

V

gV > Vfb

(a)

Ec,Ef

Ev

Ec

EfEv

(b)

M O S

qVg

depletionregion

qφs

Wdep- - - - - - -depletion layercharge, Qdep

qVox

----

- - - - - - -

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-7

5.3 Surface Depletion

ox

ssasfboxsfbg C

qNVVVV

φεφφ

2++=++=

Can this equation be solved to yield φs ?

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-9

Threshold Voltage

oxsfbg VVVV ++=

ox

BsaBfbt C

qNVV

φεφ

222 ++=

Alternative definition of the threshold condition :

V 45.0lnV 45.0 +=+=i

aBst n

Nq

kTφφ

ox

BsaBfbt C

qNVV

)V 45.0(22V 45.0

++++=

φεφ

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-10

Threshold Voltage

ox

BssubBfbt C

qNVV

φεφ

222 ±±=

Tox = 20nm

Vt(V

), N

+ −ga

te/P

-bod

y

V t(V

), P+

−gat

e/N

-bod

y

Body Doping Density (cm-3)

+ for P-body,– for N-body:

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-11

5.5 Strong Inversion–Beyond Threshold

SiO2

gate

P-Si substrate

++++++++++

V

Vg > Vt

Ec,Ef

Ev

Ec

EfEv

M O S

qVg- - - - - ---

-

- - - - - - -

-

----

Qdep Qinv

a

stsdmaxdep qN

WW φε2==Vg > Vt

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-12

Inversion Layer Charge, Qinv (C/cm2)

ox

invt

ox

inv

ox

stsastfb

ox

inv

ox

depstfbg

CQV

CQ

CqN

VCQ

CQ

VV

−=

−++=−−+=

2 φεφφ

SiO2

gate

P-body

Vg >Vt

N+SiO2

gate

P-body

Vg > Vt

N+-- - - - - - N-Si

)( tgoxinv VVCQ −−=∴

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-13

Review : Basic MOS Capacitor Theoryφs

2φs

Vfb Vt

Vgaccumulation depletion inversion

Wdep

Wdmax

accumulation depletion inversion

∝ (φs)1/2

Wdmax = (2εs2φΒ /qΝa)1/2

VgVtVfb

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-14

Review : Basic MOS Capacitor Theory

0 Vg

accumulation depletion inversion

Qinv

accumulation depletion inversion

(a)

(b)

accumulation depletion inversion

(c)

Qs

0

accumulationregime

depletionregime

inversionregime

total substrate charge, Qs

invdepaccs QQQQ ++=

Qacc

Vg

Vg

Qdep= qNaWdep

VtVfb

slope = − Cox

slope = − Cox

VtVfb

Vt

Vfb

–qNaWdep

–qNaWdmax

Vg

Qinv

slope = − Cox

Vfb

Vt

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-15

5.6 MOS CV Characteristics

g

s

g

g

dVdQ

dVdQ

C −==

~

Vg

vac

icap

CV Meter MOS Capacitor

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-16

5.6 MOS CV Characteristics

g

s

g

g

dVdQ

dVdQ

C −==

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-17

CV Characteristics

depox CCC111

+=

sa

fbg

ox qNVV

CC ε)(211

2

−+=

CCox

accumulation depletion inversionVgVfb Vt

In the depletion regime:

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-18

Cox

gate

P-substrate

-

-

-

-

- --Cdmax

Wdmax

- - - - - - -

AC

DC

+++++ + + + +

Cox

gate

P-substrate

Cox

gate

P-substrate

- - - - - -Cdep Wdep

Cox

gate

P-substrate

-

Wdmax

- - - - - - -N+

DC and AC

Supply of Inversion Charge May be Limited

Accumulation Depletion

InversionInversion

In each case, C = ?

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-19

Capacitor and Transistor CV (or HF and LF CV)

C

Vfb Vt

Cox

accumulation depletion inversionVg

MOS transistor CV at any f, LF

HF capacitor CV

capacitor CV, or quasi-static CV

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-20

Quasi-Static CV of MOS Capacitor

The quasi-static CV is obtained by the application of a slow linear-ramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very sensitive DC ammeter. C is calculated from Ig = C·dVg/dt. This allows sufficient time for Qinv to respond to the slow-changing Vg .

CCox

accumulation depletion inversionVgVfb Vt

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-21

(1) MOS transistor, 10kHz. (Answer: QS CV).

(2) MOS transistor, 100MHz. (Answer: QS CV).

(3) MOS capacitor, 100MHz. (Answer: HF capacitor CV).

(4) MOS capacitor, 10kHz. (Answer: HF capacitor CV).

(5) MOS capacitor, slow Vg ramp. (Answer: QS CV).

(6) MOS transistor, slow Vg ramp. (Answer: QS CV).

EXAMPLE : CV of MOS Capacitor and Transistor

Does the QS CV or the HF capacitor CV apply?

C

Vg

QS CV

HF capacitor CV

MOS transistor CV,

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-22

5.7 Oxide Charge–A Modification to Vfb and Vt

oxoxsgoxoxfbfb CQCQVV //0 −−=−= ψψ

Ef, Ec

Ev

Ec

Ef

Ev

Vfb0

gate oxide body

Ef, Ec

Ev

Ec

Ef

Ev

Vfb

gate oxide body

+ + +

− Qox/Cox

(a) (b)

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-23

Three types of oxide charge:

• Fixed oxide charge, Si+

• Mobile oxide charge, Na+

(due to sodium contamination)

• Stress-induced charge-a reliability issue

5.7 Oxide Charge–A Modification to Vfb and Vt

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-24

EXAMPLE: Interpret this measured Vfb dependence on oxide thickness. The gate electrode is N+ poly-silicon.

oxoxoxsgfb TQV εψψ /−−=Solution:

0

–0.15V

–0.3V

Tox

Vfb

10 nm 20 nm 30 nm

××

×

What does it tell us? Body work function? Doping type? Other?

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-25

from intercept V 15.0−=− sg ψψ

from slope 28 cm/C 107.1 −×=oxQ

E0, vacuum level

Ef , Ec

Ev

EcEf

Ev

ψg ψs = ψg + 0.15V

N+-Si gate Si body

-317eV 15.0 cm 10≈== − kTcd eNnNN-type substrate,

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-26

5.8 Poly-Silicon Gate Depletion–Effective Increase in Tox

Gauss’s Law

polyoxoxdpoly qNW /ε=

3/

1111

dpolyox

ox

s

dpoly

ox

ox

polyox

WT

WTCC

C

+=

+=

+=

−−

ε

εε

If Wdpoly= 15 Å, what is the effective increase in Tox?

Why is a reduction in C undesirable?

Cox

N-body

Cpoly

++ + + + + + +P+

P+ poly-Si

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-27

Effect of Poly-Gate Depletion on Qinv

)( tpolygoxinv VVCQ −−= φ

How can poly-depletion by minimized?

Wdpoly

Ec

Ef , Ev

EcEf

Ev

qφpoly

P+ -gate N-substrate

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-28

EXAMPLE : Poly-Silicon Gate DepletionVox , the voltage across a 2 nm thin oxide, is –1 V. The P+ poly-gate doping is Npoly = 8 ×1019 cm-3 and substrate Nd is 1017cm-3. Find (a) Wdpoly , (b) φpoly , and (c) Vg .

Solution:

(a)

nm3.1cm108C106.1cm102

V1)F/cm(1085.89.3

//

319197

14

=×⋅×⋅×

⋅××=

==

−−−

−

polyoxoxoxpolyoxoxdpoly qNTVqNW εε

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-29

(b)poly

polysdpoly qN

Wφε2

=

V 11.02/2 == sdpolypolydpoly WqN εφ

(c)

V 01.1V 11.0V 1V 85.0V 95.0

V 95.0V 15.0 V 1.1ln

−=−−−=

=−=

−=

+++=

g

d

cgfb

polyoxstfbg

VNN

qkT

qE

V

VVV φφ

Is the loss of 0.11 V from the 1.01 V significant?

EXAMPLE : Poly-Silicon Gate Depletion

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-30

5.9 Inversion and Accumulation Charge-Layer Thickness–Quantum Mechanical Effect

Average inversion-layer location below the Si/SiO2 interface is called the inversion-layer thickness, Tinv .

What equations need to be solved to find n(x)?Does Tinv change with varying Vg ?

-50 -40 -30 -20 -10 0 10 20 30 40 50 A

Electron Density

Quantummechanical theory

SiO2poly-Sidepletionregion

gate

Physical Tox

effective Tox

Å

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-31

Electrical Oxide Thickness, Toxe

3/3/ invdpolyoxoxe TWTT ++= at Vg=Vdd

(Vg + Vt)/Tox can be shown to be the average electric field in the inversion layer. Tinv of holes is larger than that of electrons because of difference in effective mass.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-32

Which is worse in C reduction : P+-poly over N-body or N+-poly over P-body?

Effective Oxide Thickness and Effective Oxide Capacitance

3/3/ invdpolyoxoxe TWTT ++=

)( tgoxeinv VVCQ −=

CBasic CV

with poly-depletion

with poly-depletion andcharge-layer thickness

Vg

data

Cox

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-33

5.10 CCD Imager

Deep depletion, Qinv= 0 Exposed to light

+

---

(a) (b)

-Ec Ec

Ec , EfEc , Ef

Ef EfEv

EvEv

Ev

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-34

CCD Charge Transfer

P-Si

oxide

V2

- - -- - - -- - - - --- -depletion region

P-Si

oxide- - -- - - -- depletion region

P-Si

oxide- - -- - - -- depletion region

(a)

(b)

(c)

V1 > V2 = V3

V1

V2

V3

V1 V3 V1 V2 V3 V1V2 > V1 > V3

V2 > V1 = V3

V1 V2 V3 V1 V2 V3 V1

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-35

5.11 Chapter Summary

N-type device: N+-polysilicon gate over P-body

P-type device: P+-polysilicon gate over N-body

)/( oxoxoxsgfb TCQV −−= ψψ

)(/

)(

polyoxssfb

polyoxsfbg

CQV

VVV

φφ

φφ

+−+=

+++=

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-36

i

subB n

Nq

kT ln=φ

Bst φφ 2±= )V 45.0( +± Bφor

ox

stssubstfbt C

qNVV

||2 φεφ ±+=

+ : N-type device, – : P-type device

5.11 Chapter Summary

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-37

N-type Device(N+-gate over P-substrate)

P-type Device(P+-gate over N-substrate)

What’s the diagram like at Vg > Vt ? at Vg= 0?

Ef

Ef

Vg=Vfb<0

Ef

Ef

Vg=Vfb>0 Flat-band

Ef

Vg=Vt>0

Ef

Ef

Ef

Vg=Vt<0 Threshold

5.11 Chapter Summary

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5-38

What is the root cause of the low C in the HF CV branch?

5.11 Chapter Summary

Vg

N-type Device(N+-gate over P-substrate)

P-type Device(P+-gate over N-substrate)

Vg

QS CVTransistor CV

Capacitor (HF) CV