Post on 22-Mar-2016
description
Ch 8. Sequential logic design practices
1. Documentation standards
▶ general requirements : signal name , logic symbol , schematic logic
- state machine layout : a collection of F/F & combination logic on same- flip-flops : type , function , clocking behavior- state machine description : state table/diagram, transition list text files in
H/W description language (VHDL)- Cascaded elements.- timing diagrams- timing spec : max.clock freq , set-up & hold time
min. pulse width
8.1.4 Timing Diagrams and Specification
setup time margin = tclk – tffpd(max) – tcomb(max) – tsetup
hold time margin = tffpd(min) + tcomb(min) + thold
< Table 8 –1> Propagation delay in ns of selected CMOS flip-flops, registers , and latches
8.1.4 Timing Diagrams and Specification
8.1.4 Timing Diagrams and Specification
8.1.4 Timing Diagrams and Specification
2. Latch & flip flops8.2.1 SSI Latches and flip flops
8.2.2 Switch debouncing
8.2.3 The Simplest Switch debounder
8.2.3 The Simplest Switch debounder
8.2.4 Bus Holder Circuit
Low & high -> floatingLow <-> highSource or sink a small amountof additional current through R
If pull-up resistor is too high, slow transitionIf pull-up resistor is too low, too much current
8.2.5 Multiple Registers and Latches
8.2.5 Multiple Registers and Latches
8.2.5 Multiple Registers and Latches
8.2.5 Multiple Registers and Latches
8.2.5 Multiple Registers and Latches
8.2.5 Multiple Registers and Latches
If EN_L = 1, Q <- QIf EN_L = 0, Q <- P
8.2.6 Registers and Latches in ABEL and PLDs
Data1 in Rom is readData2 in a different device is read
8.2.6 Registers and Latches in ABEL and PLDs
8.2.6 Registers and Latches in ABEL and PLDs
8.2.7 Registers and Latches in VHDL
8.2.7 Registers and Latches in VHDL
< Figure 7-12 D latch >
8.2.7 Registers and Latches in VHDL
- Inferred latch- The code doesn’t say what to do if C ≠ 1,- The compiler infers a latch to retain the value of Q
8.2.7 Registers and Latches in VHDL
8.2.7 Registers and Latches in VHDL
< Fig 8-3 >
8.2.7 Registers and Latches in VHDL
D
CLKEN
Q
CLK
clear’
IQ
CLR’
CLK
CLKEN
OE’
16
3. Sequential PLD8.3.1 Sequential GAL Devices
8.3.1 Sequential GAL Devices
8.3.1 Sequential GAL Devices
- No architecture control bits- More product terms 8-16 terms- Two more inputs
8.3.1 Sequential GAL Devices
8.3.1 Sequential GAL Devices
8.3.2 PLD Timing Specification
ㆍ A series PLD (ex : PAL26L8A ): tPD = 25n , tCO =15n, tSU = 25 nsec
ㆍ Suffix : -5 , -7 , A, B,…
8.3.2 PLD Timing Specification
ㆍ tPD : propagation delay from input to outputㆍ tCO : P-delay from rising edge of clock to outputㆍ tSU (set-up), tcf( = tCO ), tH ( hold) fmax : reliable max.freqㆍ external PLD : PLD output -> connect to input of another PLDㆍ internal PLD : same PLD
4. Counters
state diagram = single cycles
Ripple counter
ㆍ connect in series or cascaded f/fㆍ Carry : ripples from LSB to MSB one bit at a time ㆍ slow : n * tPTQ ( propagation delay of T f/f)
CLK : applied to LSB F/F only
8.4.1 Ripple Counters
8.4.2 Synchronous Counters
8.4.2 Synchronous Counters
- MSI counter : Modulus N counter/divider i) Sync : ㆍ binary 4 bit counter ( 161,163 ) 161 : Async. clear function
163 : Sync. clear ( fully sync. counter ) ㆍ decade counter : 160, 162ex) modulo-10 counter wavefarm < Fig 31> ㆍ 4 bit up/down counter :SN74169(TTL), 74C169(CMOS), CD40169(CMOS)up/down decade counter : 192
ii ) Async : ㆍ 4 bit binary counter : 193 ㆍ 12 counter : 92 ㆍ decade counter : 90 ㆍ 4 bit up/down counter : 191 ㆍ decade up/down counter : 190
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
RCO = 1 when OA = OB = OC = OD = 1 & ENT = 1
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.3 MSI Counters and Applications
8.4.6 Counters in VHDL
8.4.6 Counters in VHDL
8.4.6 Counters in VHDL
8.4.6 Counters in VHDL
8.4.6 Counters in VHDL
5. Shift Register8.5.1 Shift Register Structure
8.5.1 Shift Register Structure
8.5.2 MSI Shift Register
8.5.2 MSI Shift Register
ㆍ 4 bit bidirectional parallel-in, parallel-out shift register
= universal shift register ( shift left & right, parallel & serial in-out combination )ㆍ left ( QD -> QA ) & right ( QA -> QD) Rin ( right – in ) & Lin ( left – in )
8.5.2 MSI Shift Register
8.5.3 Shift Register Counters
S1S0 = 10RESET = 1, 0001 load then RESET = Ø = SØ
8.5.3 Shift Register Counters
8.5.3 Shift Register Counters
8.5.4 Ring Counters
If Q0, Q1, Q2=1, then Ø to LIN
If Q0, Q1, Q2=0, then 1 to LIN
8.5.4 Ring Counters
8.5.4 Ring Counters
If Q0, Q1, Q2=1, LIN = ØElse LIN = 1when RESET, 1110 load
8.5.4 Ring Counters
RESET = Ø = CLR, Q3Q2Q1Q0 = 0000
If Q3 = Ø, LIN = 1If Q3 = 1, LIN = Ø
8.5.4 Ring Counters
8.5.5 Johnson Counters
D Q D Q D Q
CLK
•••Q
: Twisted ring counter 2n : 1 scalar Ex) if n=4, 8 states • Simple decoding logic Ex) 4 bit Johnson counter [ ref binary counter ]
8.5.5 Johnson Counters
2n – 2n abnormal states
OXXO -> 0001Then LOAD 0001
N = 4, 24 – 2x4 = 8(abnormal states)
If Q3 = 0, LIN = 1If Q3 = 1, LIN = Ø
8.5.5 Johnson Counters
8.5.6 Linear Feedback Shift Register Counters
8.5.6 Linear Feedback Shift Register Counters
8.5.6 Linear Feedback Shift Register Counters
8.5.6 Linear Feedback Shift Register Counters
8.5.7 Shift Register in ABEL and PLDs
8.5.8 Ring Counter in ABEL and PLDs
8.5.8 Ring Counter in ABEL and PLDs
8.5.8 Shift Register in VHDL
8.5.8 Shift Register in VHDL
8.5.8 Shift Register in VHDL
8.5.8 Shift Register in VHDL
8.5.8 Shift Register in VHDL
6. Iterative versus Sequential Circuits
If X = Y, A = 1, EQI = 1, -> then EQO = 1If X ≠ Y, A = 0, EQI = 1, -> then EQO = Ø
RESET_L = Ø EQO = 1, next clock EQI = 1
design goal for the digital systems ⅰ) function as required ⅱ) high reliable & easy maintenance ⅲ) cost effective design factor for the reliable digital systems • clock skew & gating the clock • static , dynamic , function hazards
7. Synchronous Design Methodology
8.7.1 Synchronous System Structure
8.7.1 Synchronous System Structure
▶ design factor for reliable digital systems ⅰ) clock skew ⅱ) gating the clock 1) clock skew difference between arrival times (of a clock at different devices) - for proper operation tffpd(min) + tcomg(min) - thold – tskew(max) > 0 if hold time margin > clock skew, then system → OK
8. Impediments to Synchronous Design
8.8.1 Clock Skew
8.8.1 Clock Skew
8.8.1 Clock Skew
8.8.1 Clock Skew
8.8.2 Gating the Clock
If CLKEN = Ø, GCLK = 1 (not ticking)If CLKEN = 1, GCLK = Clock_L = Clock
8.8.2 Gating the Clock
8.8.3 Asynchronous Inputs
8.8.3 Asynchronous Inputs
8.8.3 Asynchronous Inputs
8.8.3 Asynchronous Inputs
▶ metastable : Set-up & hold time → violation (not meet) ▶ Synchronizer failure - if system → use synchronizer output, while output → metastable output solution ⅰ) min. pulse width , set-up time ⅱ) wait “ long enough” until f/f → come out of metastable ▶ metastability resolution time : tr
tr = tclk – tcomb – tsetup ▶ reliable synchronous design ⅰ) wait “long enough” → slow down ⅱ) for speed up use
9. Synchronizer Failure and Metastability
8.9.1 Synchronizer Failure
8.9.3 Reliable Synchronizer Design
8.9.3 Reliable Synchronizer Design
8.9.5 Better Synchronizers
8.9.5 Better Synchronizers
8.9.6 Other Synchronizer Designs
8.9.6 Other Synchronizer Designs
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers
8.9.7 Synchronizing High-Speed Data Transfers