Post on 05-Mar-2021
General DescriptionThe MAX11600ndashMAX11605 low-power 8-bit multichan-nel analog-to-digital converters (ADCs) feature internaltrackhold (TH) voltage reference clock and an I2C-compatible 2-wire serial interface These devicesoperate from a single supply and require only 350microA atthe maximum sampling rate of 188ksps Auto-Shutdowntrade powers down the devices between conver-sions reducing supply current to less than 1microA at lowthroughput rates The MAX11600MAX11601 provide 4analog input channels each the MAX11602MAX11603provide 8 analog input channels each while theMAX11604MAX11605 provide 12 analog input channelsThe analog inputs are software configurable for unipolar orbipolar and single-ended or pseudo-differential operation
The full-scale analog input range is determined by theinternal reference or by an externally applied referencevoltage ranging from 1V to VDD The MAX11601MAX11603MAX11605 feature a 2048V internal refer-ence and the MAX11600MAX11602MAX11604 featurea 4096V internal reference
The MAX11600MAX11601 are available in 8-pin SOT23packages The MAX11602ndashMAX11605 are available in16-pin QSOP packages The MAX11600ndashMAX11605 areguaranteed over the extended industrial temperaturerange (-40degC to +85degC) Refer to the MAX11606ndashMAX11611 for 10-bit devices and to the MAX11612ndashMAX11617 for 12-bit devices
ApplicationsHandheld Portable ApplicationsMedical InstrumentsBattery-Powered Test EquipmentSolar-Powered Remote SystemsReceived-Signal-Strength IndicatorsSystem Supervision
Features High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode17MHz High-Speed Mode
Single Supply27V to 36V (MAX11601MAX11603MAX11605)45V to 55V (MAX11600MAX11602MAX11604)
Internal Reference2048V (MAX11601MAX11603MAX11605)4096V (MAX11600MAX11602MAX11604)
External Reference 1V to VDD
Internal Clock 4-Channel Single-Ended or 2-Channel Pseudo-
Differential (MAX11600MAX11601) 8-Channel Single-Ended or 4-Channel Pseudo-
Differential (MAX11602MAX11603) 12-Channel Single-Ended or 6-Channel Pseudo-
Differential (MAX11604MAX11605) Internal FIFO with Channel-Scan Mode Low Power
350microA at 188ksps110microA at 75ksps8microA at 10ksps1microA in Power-Down Mode
Software Configurable UnipolarBipolar Small Packages
8-Pin SOT23 (MAX11600MAX11601)16-Pin QSOP (MAX11602ndashMAX11605)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
________________________________________________________________ Maxim Integrated Products 1
Ordering InformationSelector Guide
19-4554 Rev 2 310
PART TEMP RANGE PIN-PACKAGETUE
(LSB)INPUT
CHANNELSINTERNAL
REFERENCE (V)TOP
MARK
MAX11600EKA+ -40degC to +85degC 8 SOT23 plusmn2 4 4096 AEQH
MAX11601EKA+ -40degC to +85degC 8 SOT23 plusmn2 4 2048 AEQI
MAX11602EEE+ -40degC to +85degC 16 QSOP plusmn1 8 4096 mdash
MAX11603EEE+ -40degC to +85degC 16 QSOP plusmn1 8 2048 mdash
MAX11604EEE+ -40degC to +85degC 16 QSOP plusmn1 12 4096 mdash
MAX11605EEE+ -40degC to +85degC 16 QSOP plusmn1 12 2048 mdash
+Denotes a lead(Pb)-freeRoHS-compliant packageAutoShutdown is a trademark of Maxim Integrated Products Inc
Pin Configurations and Typical Operating Circuit appear at end of data sheet
EVALUATION KIT
AVAILABLE
For pricing delivery and ordering information please contact Maxim Direct at 1-888-629-4642or visit Maxims website at wwwmaxim-iccom
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
Stresses beyond those listed under ldquoAbsolute Maximum Ratingsrdquo may cause permanent damage to the device These are stress ratings only and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure toabsolute maximum rating conditions for extended periods may affect device reliability
VDD to GND-03V to +6VAIN0ndashAIN11 REF to
GND -03V to the lower of (VDD + 03V) and +6V SDA SCL to GND-03V to +6VMaximum Current into Any Pin plusmn50mAContinuous Power Dissipation (TA = +70degC)
8-Pin SOT23 (derate 71mWdegC above +70degC)567mW16-Pin QSOP (derate 83mWdegC above +70degC)6667mW
Operating Temperature Range -40degC to +85degCJunction Temperature +150degCStorage Temperature Range -60degC to +150degCLead Temperature (soldering 10s) +300degCSoldering Temperature (reflow) +260degC
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 8 Bits
Relative Accuracy INL (Note 2) plusmn1 LSB
Differential Nonlinearity DNL No missing codes over temperature plusmn1 LSB
Offset Error plusmn15 LSB
Offset-Error TemperatureCoefficient
3 ppmdegC
Gain Error (Note 3) plusmn1 LSB
Gain Temperature Coefficient plusmn1 ppmdegC
MAX11600MAX11601 plusmn05 plusmn2
MAX11602MAX11603 plusmn05 plusmn1Total Unadjusted Error TUE
MAX11604MAX11605 plusmn05 plusmn1
LSB
Channel-to-Channel OffsetMatching
plusmn01 LSB
Channel-to-Channel GainMatching
plusmn05 LSB
Input Common-Mode RejectionRatio
CMRR Pseudo-differential input mode 75 dB
DYNAMIC PERFORMANCE (fIN(sine wave) = 25kHz VIN = VREF(P-P) fSAMPLE = 188ksps RIN = 100Ω)
Signal-to-Noise Plus Distortion SINAD 49 dB
Total Harmonic Distortion THD Up to the 5th harmonic -69 dB
Spurious-Free Dynamic Range SFDR 69 dB
Channel-to-Channel Crosstalk (Note 4) 75 dB
Full-Power Bandwidth -3dB point 20 MHz
Full-Linear Bandwidth SINAD gt 49dB 200 kHz
CONVERSION RATE
Internal clock 61Conversion Time (Note 5) tCONV
External clock 47micros
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Internal clock SCAN[10] = 01(MAX11600MAX11601)
76
SCAN[10] = 00 CS[30] = 0111(MAX11602MAX11603)
76
Internal clock SCAN[10] = 00CS[30] = 1011 (MAX11604MAX11605)
77
Throughput Rate fSAMPLE
External clock 188
ksps
TrackHold Acquisition Time 588 ns
Internal Clock Frequency 225 MHz
External clock fast mode 45Aperture Delay tAD
External clock high-speed mode 30ns
ANALOG INPUT (AIN0ndashAIN11)
Unipolar 0 VREFInput Voltage Range SingleEnded and Differential (Note 6) Bipolar plusmnVREF2
V
Input Multiplexer Leakage CurrentOnoff-leakage current VAIN_ = 0 or VDDno clock fSCL = 0
plusmn001 plusmn1 microA
Input Capacitance CIN 18 pF
INTERNAL REFERENCE (Note 7)
M AX11601M AX 11603MAX 11605 1925 2048 2171Reference Voltage VREF TA = +25degC
M AX11600M AX 11602MAX 11604 3850 4096 4342V
Reference TemperatureCoefficient
TCREF 120 ppmdegC
Reference Short-Circuit Current 10 mA
Reference Source Impedance (Note 8) 675 ΩEXTERNAL REFERENCE
Reference Input Voltage Range VREF (Note 9) 10 VDD V
REF Input Current IREF fSAMPLE = 188ksps 14 30 microA
DIGITAL INPUTSOUTPUTS (SCL SDA)
Input High Voltage VIH 07 x VDD V
Input Low Voltage VIL 03 x VDD V
Input Hysteresis VHYST 01 x VDD V
Input Current IIN VIN = 0 to VDD plusmn10 microA
Input Capacitance CIN 15 pF
Output Low Voltage VOL ISINK = 3mA 04 V
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
MAX11601MAX11603MAX11605 27 36Supply Voltage (Note 10) VDD
MAX11600MAX11602MAX11604 45 55V
Internal REF external clock 350 650fSAMPLE =188ksps External REF external clock 250
External REF external clock 110fSAMPLE =75ksps External REF internal clock 150
External REF external clock 8fSAMPLE =10ksps External REF internal clock 10
External REF external clock 2fSAMPLE =1ksps External REF internal clock 25
Supply Current IDD
Power-down 1 10
microA
Power-Supply Rejection Ratio PSRR (Note 11) plusmn025 plusmn1 LSBV
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency fSCL 400 kHz
Bus Fr ee Ti m e Betw een a S TO P ( P ) and a S TART ( S ) C ond i ti on
tBUF 13 micros
Hold Time for START Condition tHDSTA 06 micros
Low Period of the SCL Clock tLOW 13 micros
High Period of the SCL Clock tHIGH 06 micros
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 06 micros
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 100 ns
Rise Time of Both SDA and SCLSignals Receiving
tR (Note 13) 20 + 01CB 300 ns
Fall Time of SDA Transmitting tF (Note 13) 20 + 01CB 300 ns
Setup Time for STOP Condition tSUSTO 06 micros
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 50 ns
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency fSCLH (Note 14) 17 MHz
Hold Time (Repeated) STARTCondition
tHDSTA 160 ns
Low Period of the SCL Clock tLOW 320 ns
High Period of the SCL Clock tHIGH 120 ns
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 160 ns
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 10 ns
Rise Time of SCL Signal(Current Source Enabled)
tRCL (Note 13) 20 80 ns
Rise Time of SCL Signal AfterAcknowledge Bit
tRCL1 (Note 13) 20 160 ns
Fall Time of SCL Signal tFCL (Note 13) 20 80 ns
Rise Time of SDA Signal tRDA (Note 13) 20 160 ns
Fall Time of SDA Signal tFDA (Note 13) 20 160 ns
Setup Time for STOP Condition tSU STO 160 ns
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 0 10 ns
Note 1 The MAX11600MAX11602MAX11604 are tested at VDD = 5V and the MAX11601MAX11603MAX11605 are tested at VDD= 3V All devices are configured for unipolar single-ended inputs
Note 2 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range andoffsets have been calibrated
Note 3 Offset nulledNote 4 Ground on channel sine wave applied to all off channelsNote 5 Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period Conversion time does not
include acquisition time SCL is the conversion clock in the external clock modeNote 6 The absolute voltage range for the analog inputs (AIN0ndashAIN11) is from GND to VDDNote 7 When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) is configured to be an inter-
nal reference (SEL[21] = 11) decouple AIN_REF or REF to GND with a 001microF capacitorNote 8 The switch connecting the reference buffer to AIN_REF or REF has a typical on-resistance of 675ΩNote 9 ADC performance is limited by the converterrsquos noise floor typically 14mVP-P Note 10 Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX) For operation beyond this range see the Typical
Operating CharacteristicsNote 11 Power-supply rejection ratio is measured as
for the MAX11601MAX11603MAX11605 where N is the number of bitsPower-supply rejection ratio is measured as
for the MAX11600MAX11602MAX11604 where N is the number of bits
Note 12 A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region ofSCLrsquos falling edge (Figure 1)
Note 13 CB = total capacitance of one bus line in pF tR tFDA and tF measured between 03VDD and 07VDD The minimum value isspecified at TA = +25degC with CB = 400pF
Note 14 fSCLH must meet the minimum clock low time plus the risefall times
V V V VV
V V
FS FS
N
REF5 5 4 5
2
5 5 4 5
( ) minus ( )[ ] times
minus
V V V VV
V V
FS FS
N
REF3 3 2 7
2
3 3 2 7
( ) minus ( )[ ] times
minus
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
6 _______________________________________________________________________________________
Typical Operating Characteristics(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
150
250
200
350
300
400
450
SUPPLY CURRENT vs VOLTAGE
MAX
1160
0 to
c01
VDD (V)
I DD
(microA)
25 35 4030 45 50 55
A) INTERNAL 4096VREFB) INTERNAL 2048VREFC) EXTERNAL 4096VREFD) EXTERNAL 2048VREF
A
C
B
D
150
250
200
350
300
400
450
-40 85
SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c02
TEMPERATURE (degC)
I DD
(microA)
10-15 35 60
INTERNAL 4096VREF
INTERNAL 2048VREF
EXTERNAL 4096VREF
EXTERNAL 2048VREF
0
1
3
2
4
5
25 3530 40 45 50 55
SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
MAX
1160
0 to
c03
VDD (V)
I DD
(microA)
SDA = SCL = VDD
0
1
3
2
4
5
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c04
TEMPERATURE (degC)
I DD
(microA)
SDA = SCL = VDD
VDD = 5V
VDD = 33V0
100
50
200
150
300
250
350
0 20 3010 40 50 60
AVERAGE SUPPLY CURRENT vs CONVERSION RATE (INTERNAL CLOCK)
MAX
1160
0 to
c05
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
A
C
B
INTERNAL CLOCK MODEfSCL = 17MHz
0
150
100
50
300
250
200
450
400
350
500
0 10050 150 200
AVERAGE SUPPLY CURRENT VS CONVERSION RATE (EXTERNAL CLOCK)
MAX
1160
0 to
c06
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A
C
B
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
EXTERNAL CLOCK MODEfSCL = 17MHz
09900
09925
09950
09975
10000
10025
10050
10075
10100
400 450425 475 500 525 550
NORMALIZED 4096V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c7
VDD (V)
V REF
NOR
MAL
IZED
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 4096V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c08
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
09900
09925
09950
09975
10000
10025
10050
10075
10100
25 3530 40 45 50 55
INTERNAL 2048V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c09
VDD (V)
V REF
NOR
MAL
IZED
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 2048V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c10
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
DIFFERENTIAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c11
DIGITAL OUTPUT CODE
DNL
(LSB
)
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
INTEGRAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c12
DIGITAL OUTPUT CODE
INL
(LSB
)
-120
-80
-100
-40
-60
-20
0
0 100k
FFT PLOT
MAX
1160
0 to
c13
FREQUENCY (Hz)
AMPL
ITUD
E (d
Bc)
40k20k 60k 80k
fSAMPLE = 188kspsfIN = 25kHz
0
03
02
01
04
05
06
07
08
09
10
25 3530 40 45 50 55
OFFSET ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c14
VDD (V)
OFFS
ET E
RROR
(LS
B)
VREF = 2048V
0
03
02
01
04
05
06
07
08
09
10
-40 10-15 35 60 85
OFFSET ERROR vs TEMPERATURE
MAX
1160
0 to
c15
TEMPERATURE (degC)
OFFS
ET E
RROR
(LS
B)
VDD = 33VVREF = 2048V
-01
-007
-008
-009
-006
-005
-004
-003
-002
-001
0
25 3530 40 45 50 55
GAIN ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c16
VDD (V)
GAIN
ERR
OR (
LSB)
VREF = 2048V
Typical Operating Characteristics (continued)(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
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Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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05 SCL is high (Figure 5) A repeated START condition (Sr)
can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
MA
X1
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00
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05
random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
MA
X1
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00
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16
05
Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
MA
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
Stresses beyond those listed under ldquoAbsolute Maximum Ratingsrdquo may cause permanent damage to the device These are stress ratings only and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure toabsolute maximum rating conditions for extended periods may affect device reliability
VDD to GND-03V to +6VAIN0ndashAIN11 REF to
GND -03V to the lower of (VDD + 03V) and +6V SDA SCL to GND-03V to +6VMaximum Current into Any Pin plusmn50mAContinuous Power Dissipation (TA = +70degC)
8-Pin SOT23 (derate 71mWdegC above +70degC)567mW16-Pin QSOP (derate 83mWdegC above +70degC)6667mW
Operating Temperature Range -40degC to +85degCJunction Temperature +150degCStorage Temperature Range -60degC to +150degCLead Temperature (soldering 10s) +300degCSoldering Temperature (reflow) +260degC
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 8 Bits
Relative Accuracy INL (Note 2) plusmn1 LSB
Differential Nonlinearity DNL No missing codes over temperature plusmn1 LSB
Offset Error plusmn15 LSB
Offset-Error TemperatureCoefficient
3 ppmdegC
Gain Error (Note 3) plusmn1 LSB
Gain Temperature Coefficient plusmn1 ppmdegC
MAX11600MAX11601 plusmn05 plusmn2
MAX11602MAX11603 plusmn05 plusmn1Total Unadjusted Error TUE
MAX11604MAX11605 plusmn05 plusmn1
LSB
Channel-to-Channel OffsetMatching
plusmn01 LSB
Channel-to-Channel GainMatching
plusmn05 LSB
Input Common-Mode RejectionRatio
CMRR Pseudo-differential input mode 75 dB
DYNAMIC PERFORMANCE (fIN(sine wave) = 25kHz VIN = VREF(P-P) fSAMPLE = 188ksps RIN = 100Ω)
Signal-to-Noise Plus Distortion SINAD 49 dB
Total Harmonic Distortion THD Up to the 5th harmonic -69 dB
Spurious-Free Dynamic Range SFDR 69 dB
Channel-to-Channel Crosstalk (Note 4) 75 dB
Full-Power Bandwidth -3dB point 20 MHz
Full-Linear Bandwidth SINAD gt 49dB 200 kHz
CONVERSION RATE
Internal clock 61Conversion Time (Note 5) tCONV
External clock 47micros
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Internal clock SCAN[10] = 01(MAX11600MAX11601)
76
SCAN[10] = 00 CS[30] = 0111(MAX11602MAX11603)
76
Internal clock SCAN[10] = 00CS[30] = 1011 (MAX11604MAX11605)
77
Throughput Rate fSAMPLE
External clock 188
ksps
TrackHold Acquisition Time 588 ns
Internal Clock Frequency 225 MHz
External clock fast mode 45Aperture Delay tAD
External clock high-speed mode 30ns
ANALOG INPUT (AIN0ndashAIN11)
Unipolar 0 VREFInput Voltage Range SingleEnded and Differential (Note 6) Bipolar plusmnVREF2
V
Input Multiplexer Leakage CurrentOnoff-leakage current VAIN_ = 0 or VDDno clock fSCL = 0
plusmn001 plusmn1 microA
Input Capacitance CIN 18 pF
INTERNAL REFERENCE (Note 7)
M AX11601M AX 11603MAX 11605 1925 2048 2171Reference Voltage VREF TA = +25degC
M AX11600M AX 11602MAX 11604 3850 4096 4342V
Reference TemperatureCoefficient
TCREF 120 ppmdegC
Reference Short-Circuit Current 10 mA
Reference Source Impedance (Note 8) 675 ΩEXTERNAL REFERENCE
Reference Input Voltage Range VREF (Note 9) 10 VDD V
REF Input Current IREF fSAMPLE = 188ksps 14 30 microA
DIGITAL INPUTSOUTPUTS (SCL SDA)
Input High Voltage VIH 07 x VDD V
Input Low Voltage VIL 03 x VDD V
Input Hysteresis VHYST 01 x VDD V
Input Current IIN VIN = 0 to VDD plusmn10 microA
Input Capacitance CIN 15 pF
Output Low Voltage VOL ISINK = 3mA 04 V
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
MAX11601MAX11603MAX11605 27 36Supply Voltage (Note 10) VDD
MAX11600MAX11602MAX11604 45 55V
Internal REF external clock 350 650fSAMPLE =188ksps External REF external clock 250
External REF external clock 110fSAMPLE =75ksps External REF internal clock 150
External REF external clock 8fSAMPLE =10ksps External REF internal clock 10
External REF external clock 2fSAMPLE =1ksps External REF internal clock 25
Supply Current IDD
Power-down 1 10
microA
Power-Supply Rejection Ratio PSRR (Note 11) plusmn025 plusmn1 LSBV
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency fSCL 400 kHz
Bus Fr ee Ti m e Betw een a S TO P ( P ) and a S TART ( S ) C ond i ti on
tBUF 13 micros
Hold Time for START Condition tHDSTA 06 micros
Low Period of the SCL Clock tLOW 13 micros
High Period of the SCL Clock tHIGH 06 micros
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 06 micros
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 100 ns
Rise Time of Both SDA and SCLSignals Receiving
tR (Note 13) 20 + 01CB 300 ns
Fall Time of SDA Transmitting tF (Note 13) 20 + 01CB 300 ns
Setup Time for STOP Condition tSUSTO 06 micros
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 50 ns
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency fSCLH (Note 14) 17 MHz
Hold Time (Repeated) STARTCondition
tHDSTA 160 ns
Low Period of the SCL Clock tLOW 320 ns
High Period of the SCL Clock tHIGH 120 ns
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 160 ns
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 10 ns
Rise Time of SCL Signal(Current Source Enabled)
tRCL (Note 13) 20 80 ns
Rise Time of SCL Signal AfterAcknowledge Bit
tRCL1 (Note 13) 20 160 ns
Fall Time of SCL Signal tFCL (Note 13) 20 80 ns
Rise Time of SDA Signal tRDA (Note 13) 20 160 ns
Fall Time of SDA Signal tFDA (Note 13) 20 160 ns
Setup Time for STOP Condition tSU STO 160 ns
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 0 10 ns
Note 1 The MAX11600MAX11602MAX11604 are tested at VDD = 5V and the MAX11601MAX11603MAX11605 are tested at VDD= 3V All devices are configured for unipolar single-ended inputs
Note 2 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range andoffsets have been calibrated
Note 3 Offset nulledNote 4 Ground on channel sine wave applied to all off channelsNote 5 Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period Conversion time does not
include acquisition time SCL is the conversion clock in the external clock modeNote 6 The absolute voltage range for the analog inputs (AIN0ndashAIN11) is from GND to VDDNote 7 When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) is configured to be an inter-
nal reference (SEL[21] = 11) decouple AIN_REF or REF to GND with a 001microF capacitorNote 8 The switch connecting the reference buffer to AIN_REF or REF has a typical on-resistance of 675ΩNote 9 ADC performance is limited by the converterrsquos noise floor typically 14mVP-P Note 10 Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX) For operation beyond this range see the Typical
Operating CharacteristicsNote 11 Power-supply rejection ratio is measured as
for the MAX11601MAX11603MAX11605 where N is the number of bitsPower-supply rejection ratio is measured as
for the MAX11600MAX11602MAX11604 where N is the number of bits
Note 12 A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region ofSCLrsquos falling edge (Figure 1)
Note 13 CB = total capacitance of one bus line in pF tR tFDA and tF measured between 03VDD and 07VDD The minimum value isspecified at TA = +25degC with CB = 400pF
Note 14 fSCLH must meet the minimum clock low time plus the risefall times
V V V VV
V V
FS FS
N
REF5 5 4 5
2
5 5 4 5
( ) minus ( )[ ] times
minus
V V V VV
V V
FS FS
N
REF3 3 2 7
2
3 3 2 7
( ) minus ( )[ ] times
minus
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
6 _______________________________________________________________________________________
Typical Operating Characteristics(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
150
250
200
350
300
400
450
SUPPLY CURRENT vs VOLTAGE
MAX
1160
0 to
c01
VDD (V)
I DD
(microA)
25 35 4030 45 50 55
A) INTERNAL 4096VREFB) INTERNAL 2048VREFC) EXTERNAL 4096VREFD) EXTERNAL 2048VREF
A
C
B
D
150
250
200
350
300
400
450
-40 85
SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c02
TEMPERATURE (degC)
I DD
(microA)
10-15 35 60
INTERNAL 4096VREF
INTERNAL 2048VREF
EXTERNAL 4096VREF
EXTERNAL 2048VREF
0
1
3
2
4
5
25 3530 40 45 50 55
SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
MAX
1160
0 to
c03
VDD (V)
I DD
(microA)
SDA = SCL = VDD
0
1
3
2
4
5
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c04
TEMPERATURE (degC)
I DD
(microA)
SDA = SCL = VDD
VDD = 5V
VDD = 33V0
100
50
200
150
300
250
350
0 20 3010 40 50 60
AVERAGE SUPPLY CURRENT vs CONVERSION RATE (INTERNAL CLOCK)
MAX
1160
0 to
c05
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
A
C
B
INTERNAL CLOCK MODEfSCL = 17MHz
0
150
100
50
300
250
200
450
400
350
500
0 10050 150 200
AVERAGE SUPPLY CURRENT VS CONVERSION RATE (EXTERNAL CLOCK)
MAX
1160
0 to
c06
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A
C
B
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
EXTERNAL CLOCK MODEfSCL = 17MHz
09900
09925
09950
09975
10000
10025
10050
10075
10100
400 450425 475 500 525 550
NORMALIZED 4096V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c7
VDD (V)
V REF
NOR
MAL
IZED
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 4096V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c08
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
09900
09925
09950
09975
10000
10025
10050
10075
10100
25 3530 40 45 50 55
INTERNAL 2048V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c09
VDD (V)
V REF
NOR
MAL
IZED
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 2048V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c10
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
DIFFERENTIAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c11
DIGITAL OUTPUT CODE
DNL
(LSB
)
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
INTEGRAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c12
DIGITAL OUTPUT CODE
INL
(LSB
)
-120
-80
-100
-40
-60
-20
0
0 100k
FFT PLOT
MAX
1160
0 to
c13
FREQUENCY (Hz)
AMPL
ITUD
E (d
Bc)
40k20k 60k 80k
fSAMPLE = 188kspsfIN = 25kHz
0
03
02
01
04
05
06
07
08
09
10
25 3530 40 45 50 55
OFFSET ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c14
VDD (V)
OFFS
ET E
RROR
(LS
B)
VREF = 2048V
0
03
02
01
04
05
06
07
08
09
10
-40 10-15 35 60 85
OFFSET ERROR vs TEMPERATURE
MAX
1160
0 to
c15
TEMPERATURE (degC)
OFFS
ET E
RROR
(LS
B)
VDD = 33VVREF = 2048V
-01
-007
-008
-009
-006
-005
-004
-003
-002
-001
0
25 3530 40 45 50 55
GAIN ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c16
VDD (V)
GAIN
ERR
OR (
LSB)
VREF = 2048V
Typical Operating Characteristics (continued)(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
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Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
MA
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00
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X1
16
05
Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
MA
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16
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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16
05 SCL is high (Figure 5) A repeated START condition (Sr)
can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
MA
X1
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05
random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
MA
X1
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00
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16
05
Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
MA
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Internal clock SCAN[10] = 01(MAX11600MAX11601)
76
SCAN[10] = 00 CS[30] = 0111(MAX11602MAX11603)
76
Internal clock SCAN[10] = 00CS[30] = 1011 (MAX11604MAX11605)
77
Throughput Rate fSAMPLE
External clock 188
ksps
TrackHold Acquisition Time 588 ns
Internal Clock Frequency 225 MHz
External clock fast mode 45Aperture Delay tAD
External clock high-speed mode 30ns
ANALOG INPUT (AIN0ndashAIN11)
Unipolar 0 VREFInput Voltage Range SingleEnded and Differential (Note 6) Bipolar plusmnVREF2
V
Input Multiplexer Leakage CurrentOnoff-leakage current VAIN_ = 0 or VDDno clock fSCL = 0
plusmn001 plusmn1 microA
Input Capacitance CIN 18 pF
INTERNAL REFERENCE (Note 7)
M AX11601M AX 11603MAX 11605 1925 2048 2171Reference Voltage VREF TA = +25degC
M AX11600M AX 11602MAX 11604 3850 4096 4342V
Reference TemperatureCoefficient
TCREF 120 ppmdegC
Reference Short-Circuit Current 10 mA
Reference Source Impedance (Note 8) 675 ΩEXTERNAL REFERENCE
Reference Input Voltage Range VREF (Note 9) 10 VDD V
REF Input Current IREF fSAMPLE = 188ksps 14 30 microA
DIGITAL INPUTSOUTPUTS (SCL SDA)
Input High Voltage VIH 07 x VDD V
Input Low Voltage VIL 03 x VDD V
Input Hysteresis VHYST 01 x VDD V
Input Current IIN VIN = 0 to VDD plusmn10 microA
Input Capacitance CIN 15 pF
Output Low Voltage VOL ISINK = 3mA 04 V
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
MAX11601MAX11603MAX11605 27 36Supply Voltage (Note 10) VDD
MAX11600MAX11602MAX11604 45 55V
Internal REF external clock 350 650fSAMPLE =188ksps External REF external clock 250
External REF external clock 110fSAMPLE =75ksps External REF internal clock 150
External REF external clock 8fSAMPLE =10ksps External REF internal clock 10
External REF external clock 2fSAMPLE =1ksps External REF internal clock 25
Supply Current IDD
Power-down 1 10
microA
Power-Supply Rejection Ratio PSRR (Note 11) plusmn025 plusmn1 LSBV
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency fSCL 400 kHz
Bus Fr ee Ti m e Betw een a S TO P ( P ) and a S TART ( S ) C ond i ti on
tBUF 13 micros
Hold Time for START Condition tHDSTA 06 micros
Low Period of the SCL Clock tLOW 13 micros
High Period of the SCL Clock tHIGH 06 micros
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 06 micros
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 100 ns
Rise Time of Both SDA and SCLSignals Receiving
tR (Note 13) 20 + 01CB 300 ns
Fall Time of SDA Transmitting tF (Note 13) 20 + 01CB 300 ns
Setup Time for STOP Condition tSUSTO 06 micros
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 50 ns
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency fSCLH (Note 14) 17 MHz
Hold Time (Repeated) STARTCondition
tHDSTA 160 ns
Low Period of the SCL Clock tLOW 320 ns
High Period of the SCL Clock tHIGH 120 ns
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 160 ns
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 10 ns
Rise Time of SCL Signal(Current Source Enabled)
tRCL (Note 13) 20 80 ns
Rise Time of SCL Signal AfterAcknowledge Bit
tRCL1 (Note 13) 20 160 ns
Fall Time of SCL Signal tFCL (Note 13) 20 80 ns
Rise Time of SDA Signal tRDA (Note 13) 20 160 ns
Fall Time of SDA Signal tFDA (Note 13) 20 160 ns
Setup Time for STOP Condition tSU STO 160 ns
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 0 10 ns
Note 1 The MAX11600MAX11602MAX11604 are tested at VDD = 5V and the MAX11601MAX11603MAX11605 are tested at VDD= 3V All devices are configured for unipolar single-ended inputs
Note 2 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range andoffsets have been calibrated
Note 3 Offset nulledNote 4 Ground on channel sine wave applied to all off channelsNote 5 Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period Conversion time does not
include acquisition time SCL is the conversion clock in the external clock modeNote 6 The absolute voltage range for the analog inputs (AIN0ndashAIN11) is from GND to VDDNote 7 When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) is configured to be an inter-
nal reference (SEL[21] = 11) decouple AIN_REF or REF to GND with a 001microF capacitorNote 8 The switch connecting the reference buffer to AIN_REF or REF has a typical on-resistance of 675ΩNote 9 ADC performance is limited by the converterrsquos noise floor typically 14mVP-P Note 10 Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX) For operation beyond this range see the Typical
Operating CharacteristicsNote 11 Power-supply rejection ratio is measured as
for the MAX11601MAX11603MAX11605 where N is the number of bitsPower-supply rejection ratio is measured as
for the MAX11600MAX11602MAX11604 where N is the number of bits
Note 12 A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region ofSCLrsquos falling edge (Figure 1)
Note 13 CB = total capacitance of one bus line in pF tR tFDA and tF measured between 03VDD and 07VDD The minimum value isspecified at TA = +25degC with CB = 400pF
Note 14 fSCLH must meet the minimum clock low time plus the risefall times
V V V VV
V V
FS FS
N
REF5 5 4 5
2
5 5 4 5
( ) minus ( )[ ] times
minus
V V V VV
V V
FS FS
N
REF3 3 2 7
2
3 3 2 7
( ) minus ( )[ ] times
minus
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
6 _______________________________________________________________________________________
Typical Operating Characteristics(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
150
250
200
350
300
400
450
SUPPLY CURRENT vs VOLTAGE
MAX
1160
0 to
c01
VDD (V)
I DD
(microA)
25 35 4030 45 50 55
A) INTERNAL 4096VREFB) INTERNAL 2048VREFC) EXTERNAL 4096VREFD) EXTERNAL 2048VREF
A
C
B
D
150
250
200
350
300
400
450
-40 85
SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c02
TEMPERATURE (degC)
I DD
(microA)
10-15 35 60
INTERNAL 4096VREF
INTERNAL 2048VREF
EXTERNAL 4096VREF
EXTERNAL 2048VREF
0
1
3
2
4
5
25 3530 40 45 50 55
SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
MAX
1160
0 to
c03
VDD (V)
I DD
(microA)
SDA = SCL = VDD
0
1
3
2
4
5
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c04
TEMPERATURE (degC)
I DD
(microA)
SDA = SCL = VDD
VDD = 5V
VDD = 33V0
100
50
200
150
300
250
350
0 20 3010 40 50 60
AVERAGE SUPPLY CURRENT vs CONVERSION RATE (INTERNAL CLOCK)
MAX
1160
0 to
c05
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
A
C
B
INTERNAL CLOCK MODEfSCL = 17MHz
0
150
100
50
300
250
200
450
400
350
500
0 10050 150 200
AVERAGE SUPPLY CURRENT VS CONVERSION RATE (EXTERNAL CLOCK)
MAX
1160
0 to
c06
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A
C
B
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
EXTERNAL CLOCK MODEfSCL = 17MHz
09900
09925
09950
09975
10000
10025
10050
10075
10100
400 450425 475 500 525 550
NORMALIZED 4096V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c7
VDD (V)
V REF
NOR
MAL
IZED
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 4096V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c08
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
09900
09925
09950
09975
10000
10025
10050
10075
10100
25 3530 40 45 50 55
INTERNAL 2048V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c09
VDD (V)
V REF
NOR
MAL
IZED
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 2048V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c10
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
DIFFERENTIAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c11
DIGITAL OUTPUT CODE
DNL
(LSB
)
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
INTEGRAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c12
DIGITAL OUTPUT CODE
INL
(LSB
)
-120
-80
-100
-40
-60
-20
0
0 100k
FFT PLOT
MAX
1160
0 to
c13
FREQUENCY (Hz)
AMPL
ITUD
E (d
Bc)
40k20k 60k 80k
fSAMPLE = 188kspsfIN = 25kHz
0
03
02
01
04
05
06
07
08
09
10
25 3530 40 45 50 55
OFFSET ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c14
VDD (V)
OFFS
ET E
RROR
(LS
B)
VREF = 2048V
0
03
02
01
04
05
06
07
08
09
10
-40 10-15 35 60 85
OFFSET ERROR vs TEMPERATURE
MAX
1160
0 to
c15
TEMPERATURE (degC)
OFFS
ET E
RROR
(LS
B)
VDD = 33VVREF = 2048V
-01
-007
-008
-009
-006
-005
-004
-003
-002
-001
0
25 3530 40 45 50 55
GAIN ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c16
VDD (V)
GAIN
ERR
OR (
LSB)
VREF = 2048V
Typical Operating Characteristics (continued)(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
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Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
MA
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
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1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
MAX11601MAX11603MAX11605 27 36Supply Voltage (Note 10) VDD
MAX11600MAX11602MAX11604 45 55V
Internal REF external clock 350 650fSAMPLE =188ksps External REF external clock 250
External REF external clock 110fSAMPLE =75ksps External REF internal clock 150
External REF external clock 8fSAMPLE =10ksps External REF internal clock 10
External REF external clock 2fSAMPLE =1ksps External REF internal clock 25
Supply Current IDD
Power-down 1 10
microA
Power-Supply Rejection Ratio PSRR (Note 11) plusmn025 plusmn1 LSBV
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency fSCL 400 kHz
Bus Fr ee Ti m e Betw een a S TO P ( P ) and a S TART ( S ) C ond i ti on
tBUF 13 micros
Hold Time for START Condition tHDSTA 06 micros
Low Period of the SCL Clock tLOW 13 micros
High Period of the SCL Clock tHIGH 06 micros
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 06 micros
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 100 ns
Rise Time of Both SDA and SCLSignals Receiving
tR (Note 13) 20 + 01CB 300 ns
Fall Time of SDA Transmitting tF (Note 13) 20 + 01CB 300 ns
Setup Time for STOP Condition tSUSTO 06 micros
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 50 ns
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency fSCLH (Note 14) 17 MHz
Hold Time (Repeated) STARTCondition
tHDSTA 160 ns
Low Period of the SCL Clock tLOW 320 ns
High Period of the SCL Clock tHIGH 120 ns
Setup Time for a Repeated STARTCondition (Sr)
tSUSTA 160 ns
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 10 ns
Rise Time of SCL Signal(Current Source Enabled)
tRCL (Note 13) 20 80 ns
Rise Time of SCL Signal AfterAcknowledge Bit
tRCL1 (Note 13) 20 160 ns
Fall Time of SCL Signal tFCL (Note 13) 20 80 ns
Rise Time of SDA Signal tRDA (Note 13) 20 160 ns
Fall Time of SDA Signal tFDA (Note 13) 20 160 ns
Setup Time for STOP Condition tSU STO 160 ns
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 0 10 ns
Note 1 The MAX11600MAX11602MAX11604 are tested at VDD = 5V and the MAX11601MAX11603MAX11605 are tested at VDD= 3V All devices are configured for unipolar single-ended inputs
Note 2 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range andoffsets have been calibrated
Note 3 Offset nulledNote 4 Ground on channel sine wave applied to all off channelsNote 5 Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period Conversion time does not
include acquisition time SCL is the conversion clock in the external clock modeNote 6 The absolute voltage range for the analog inputs (AIN0ndashAIN11) is from GND to VDDNote 7 When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) is configured to be an inter-
nal reference (SEL[21] = 11) decouple AIN_REF or REF to GND with a 001microF capacitorNote 8 The switch connecting the reference buffer to AIN_REF or REF has a typical on-resistance of 675ΩNote 9 ADC performance is limited by the converterrsquos noise floor typically 14mVP-P Note 10 Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX) For operation beyond this range see the Typical
Operating CharacteristicsNote 11 Power-supply rejection ratio is measured as
for the MAX11601MAX11603MAX11605 where N is the number of bitsPower-supply rejection ratio is measured as
for the MAX11600MAX11602MAX11604 where N is the number of bits
Note 12 A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region ofSCLrsquos falling edge (Figure 1)
Note 13 CB = total capacitance of one bus line in pF tR tFDA and tF measured between 03VDD and 07VDD The minimum value isspecified at TA = +25degC with CB = 400pF
Note 14 fSCLH must meet the minimum clock low time plus the risefall times
V V V VV
V V
FS FS
N
REF5 5 4 5
2
5 5 4 5
( ) minus ( )[ ] times
minus
V V V VV
V V
FS FS
N
REF3 3 2 7
2
3 3 2 7
( ) minus ( )[ ] times
minus
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
6 _______________________________________________________________________________________
Typical Operating Characteristics(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
150
250
200
350
300
400
450
SUPPLY CURRENT vs VOLTAGE
MAX
1160
0 to
c01
VDD (V)
I DD
(microA)
25 35 4030 45 50 55
A) INTERNAL 4096VREFB) INTERNAL 2048VREFC) EXTERNAL 4096VREFD) EXTERNAL 2048VREF
A
C
B
D
150
250
200
350
300
400
450
-40 85
SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c02
TEMPERATURE (degC)
I DD
(microA)
10-15 35 60
INTERNAL 4096VREF
INTERNAL 2048VREF
EXTERNAL 4096VREF
EXTERNAL 2048VREF
0
1
3
2
4
5
25 3530 40 45 50 55
SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
MAX
1160
0 to
c03
VDD (V)
I DD
(microA)
SDA = SCL = VDD
0
1
3
2
4
5
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c04
TEMPERATURE (degC)
I DD
(microA)
SDA = SCL = VDD
VDD = 5V
VDD = 33V0
100
50
200
150
300
250
350
0 20 3010 40 50 60
AVERAGE SUPPLY CURRENT vs CONVERSION RATE (INTERNAL CLOCK)
MAX
1160
0 to
c05
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
A
C
B
INTERNAL CLOCK MODEfSCL = 17MHz
0
150
100
50
300
250
200
450
400
350
500
0 10050 150 200
AVERAGE SUPPLY CURRENT VS CONVERSION RATE (EXTERNAL CLOCK)
MAX
1160
0 to
c06
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A
C
B
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
EXTERNAL CLOCK MODEfSCL = 17MHz
09900
09925
09950
09975
10000
10025
10050
10075
10100
400 450425 475 500 525 550
NORMALIZED 4096V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c7
VDD (V)
V REF
NOR
MAL
IZED
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 4096V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c08
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
09900
09925
09950
09975
10000
10025
10050
10075
10100
25 3530 40 45 50 55
INTERNAL 2048V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c09
VDD (V)
V REF
NOR
MAL
IZED
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 2048V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c10
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
DIFFERENTIAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c11
DIGITAL OUTPUT CODE
DNL
(LSB
)
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
INTEGRAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c12
DIGITAL OUTPUT CODE
INL
(LSB
)
-120
-80
-100
-40
-60
-20
0
0 100k
FFT PLOT
MAX
1160
0 to
c13
FREQUENCY (Hz)
AMPL
ITUD
E (d
Bc)
40k20k 60k 80k
fSAMPLE = 188kspsfIN = 25kHz
0
03
02
01
04
05
06
07
08
09
10
25 3530 40 45 50 55
OFFSET ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c14
VDD (V)
OFFS
ET E
RROR
(LS
B)
VREF = 2048V
0
03
02
01
04
05
06
07
08
09
10
-40 10-15 35 60 85
OFFSET ERROR vs TEMPERATURE
MAX
1160
0 to
c15
TEMPERATURE (degC)
OFFS
ET E
RROR
(LS
B)
VDD = 33VVREF = 2048V
-01
-007
-008
-009
-006
-005
-004
-003
-002
-001
0
25 3530 40 45 50 55
GAIN ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c16
VDD (V)
GAIN
ERR
OR (
LSB)
VREF = 2048V
Typical Operating Characteristics (continued)(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
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Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
MA
X1
16
00
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X1
16
05 SCL is high (Figure 5) A repeated START condition (Sr)
can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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05
random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
MA
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00
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)(VDD = 27V to 36V (MAX11601MAX11603MAX11605) VDD = 45V to 55V (MAX11600MAX11602MAX11604) External referenceVREF = 2048V (MAX11601MAX11603MAX11605) VREF = 4096V (MAX11600MAX11602MAX11604) External clock fSCL =17MHz TA = TMIN to TMAX unless otherwise noted Typical values are at TA = +25degC)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time tHDDAT (Note 12) 0 150 ns
Data Setup Time tSUDAT 10 ns
Rise Time of SCL Signal(Current Source Enabled)
tRCL (Note 13) 20 80 ns
Rise Time of SCL Signal AfterAcknowledge Bit
tRCL1 (Note 13) 20 160 ns
Fall Time of SCL Signal tFCL (Note 13) 20 80 ns
Rise Time of SDA Signal tRDA (Note 13) 20 160 ns
Fall Time of SDA Signal tFDA (Note 13) 20 160 ns
Setup Time for STOP Condition tSU STO 160 ns
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 0 10 ns
Note 1 The MAX11600MAX11602MAX11604 are tested at VDD = 5V and the MAX11601MAX11603MAX11605 are tested at VDD= 3V All devices are configured for unipolar single-ended inputs
Note 2 Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range andoffsets have been calibrated
Note 3 Offset nulledNote 4 Ground on channel sine wave applied to all off channelsNote 5 Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period Conversion time does not
include acquisition time SCL is the conversion clock in the external clock modeNote 6 The absolute voltage range for the analog inputs (AIN0ndashAIN11) is from GND to VDDNote 7 When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) is configured to be an inter-
nal reference (SEL[21] = 11) decouple AIN_REF or REF to GND with a 001microF capacitorNote 8 The switch connecting the reference buffer to AIN_REF or REF has a typical on-resistance of 675ΩNote 9 ADC performance is limited by the converterrsquos noise floor typically 14mVP-P Note 10 Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX) For operation beyond this range see the Typical
Operating CharacteristicsNote 11 Power-supply rejection ratio is measured as
for the MAX11601MAX11603MAX11605 where N is the number of bitsPower-supply rejection ratio is measured as
for the MAX11600MAX11602MAX11604 where N is the number of bits
Note 12 A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region ofSCLrsquos falling edge (Figure 1)
Note 13 CB = total capacitance of one bus line in pF tR tFDA and tF measured between 03VDD and 07VDD The minimum value isspecified at TA = +25degC with CB = 400pF
Note 14 fSCLH must meet the minimum clock low time plus the risefall times
V V V VV
V V
FS FS
N
REF5 5 4 5
2
5 5 4 5
( ) minus ( )[ ] times
minus
V V V VV
V V
FS FS
N
REF3 3 2 7
2
3 3 2 7
( ) minus ( )[ ] times
minus
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
6 _______________________________________________________________________________________
Typical Operating Characteristics(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
150
250
200
350
300
400
450
SUPPLY CURRENT vs VOLTAGE
MAX
1160
0 to
c01
VDD (V)
I DD
(microA)
25 35 4030 45 50 55
A) INTERNAL 4096VREFB) INTERNAL 2048VREFC) EXTERNAL 4096VREFD) EXTERNAL 2048VREF
A
C
B
D
150
250
200
350
300
400
450
-40 85
SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c02
TEMPERATURE (degC)
I DD
(microA)
10-15 35 60
INTERNAL 4096VREF
INTERNAL 2048VREF
EXTERNAL 4096VREF
EXTERNAL 2048VREF
0
1
3
2
4
5
25 3530 40 45 50 55
SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
MAX
1160
0 to
c03
VDD (V)
I DD
(microA)
SDA = SCL = VDD
0
1
3
2
4
5
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c04
TEMPERATURE (degC)
I DD
(microA)
SDA = SCL = VDD
VDD = 5V
VDD = 33V0
100
50
200
150
300
250
350
0 20 3010 40 50 60
AVERAGE SUPPLY CURRENT vs CONVERSION RATE (INTERNAL CLOCK)
MAX
1160
0 to
c05
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
A
C
B
INTERNAL CLOCK MODEfSCL = 17MHz
0
150
100
50
300
250
200
450
400
350
500
0 10050 150 200
AVERAGE SUPPLY CURRENT VS CONVERSION RATE (EXTERNAL CLOCK)
MAX
1160
0 to
c06
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A
C
B
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
EXTERNAL CLOCK MODEfSCL = 17MHz
09900
09925
09950
09975
10000
10025
10050
10075
10100
400 450425 475 500 525 550
NORMALIZED 4096V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c7
VDD (V)
V REF
NOR
MAL
IZED
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 4096V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c08
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
09900
09925
09950
09975
10000
10025
10050
10075
10100
25 3530 40 45 50 55
INTERNAL 2048V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c09
VDD (V)
V REF
NOR
MAL
IZED
MA
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00
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05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 2048V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c10
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
DIFFERENTIAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c11
DIGITAL OUTPUT CODE
DNL
(LSB
)
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
INTEGRAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c12
DIGITAL OUTPUT CODE
INL
(LSB
)
-120
-80
-100
-40
-60
-20
0
0 100k
FFT PLOT
MAX
1160
0 to
c13
FREQUENCY (Hz)
AMPL
ITUD
E (d
Bc)
40k20k 60k 80k
fSAMPLE = 188kspsfIN = 25kHz
0
03
02
01
04
05
06
07
08
09
10
25 3530 40 45 50 55
OFFSET ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c14
VDD (V)
OFFS
ET E
RROR
(LS
B)
VREF = 2048V
0
03
02
01
04
05
06
07
08
09
10
-40 10-15 35 60 85
OFFSET ERROR vs TEMPERATURE
MAX
1160
0 to
c15
TEMPERATURE (degC)
OFFS
ET E
RROR
(LS
B)
VDD = 33VVREF = 2048V
-01
-007
-008
-009
-006
-005
-004
-003
-002
-001
0
25 3530 40 45 50 55
GAIN ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c16
VDD (V)
GAIN
ERR
OR (
LSB)
VREF = 2048V
Typical Operating Characteristics (continued)(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
MA
X1
16
00
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16
05
Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
MA
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00
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05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
MA
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16
00
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05
Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
MA
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05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
MA
X1
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00
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16
05 SCL is high (Figure 5) A repeated START condition (Sr)
can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
MA
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05
random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
MA
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
6 _______________________________________________________________________________________
Typical Operating Characteristics(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
150
250
200
350
300
400
450
SUPPLY CURRENT vs VOLTAGE
MAX
1160
0 to
c01
VDD (V)
I DD
(microA)
25 35 4030 45 50 55
A) INTERNAL 4096VREFB) INTERNAL 2048VREFC) EXTERNAL 4096VREFD) EXTERNAL 2048VREF
A
C
B
D
150
250
200
350
300
400
450
-40 85
SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c02
TEMPERATURE (degC)
I DD
(microA)
10-15 35 60
INTERNAL 4096VREF
INTERNAL 2048VREF
EXTERNAL 4096VREF
EXTERNAL 2048VREF
0
1
3
2
4
5
25 3530 40 45 50 55
SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
MAX
1160
0 to
c03
VDD (V)
I DD
(microA)
SDA = SCL = VDD
0
1
3
2
4
5
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT vs TEMPERATURE
MAX
1160
0 to
c04
TEMPERATURE (degC)
I DD
(microA)
SDA = SCL = VDD
VDD = 5V
VDD = 33V0
100
50
200
150
300
250
350
0 20 3010 40 50 60
AVERAGE SUPPLY CURRENT vs CONVERSION RATE (INTERNAL CLOCK)
MAX
1160
0 to
c05
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
A
C
B
INTERNAL CLOCK MODEfSCL = 17MHz
0
150
100
50
300
250
200
450
400
350
500
0 10050 150 200
AVERAGE SUPPLY CURRENT VS CONVERSION RATE (EXTERNAL CLOCK)
MAX
1160
0 to
c06
CONVERSION RATE (ksps)
AVER
AGE
I DD
(microA)
A
C
B
A) INTERNAL REF ALWAYS ONB) INTERNAL REF AUTOSHUTDOWNC) EXTERNAL REF
EXTERNAL CLOCK MODEfSCL = 17MHz
09900
09925
09950
09975
10000
10025
10050
10075
10100
400 450425 475 500 525 550
NORMALIZED 4096V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c7
VDD (V)
V REF
NOR
MAL
IZED
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 4096V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c08
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
09900
09925
09950
09975
10000
10025
10050
10075
10100
25 3530 40 45 50 55
INTERNAL 2048V REFERENCE VOLTAGE vs SUPPLY VOLTAGE
MAX
1160
0 to
c09
VDD (V)
V REF
NOR
MAL
IZED
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 2048V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c10
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
DIFFERENTIAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c11
DIGITAL OUTPUT CODE
DNL
(LSB
)
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
INTEGRAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c12
DIGITAL OUTPUT CODE
INL
(LSB
)
-120
-80
-100
-40
-60
-20
0
0 100k
FFT PLOT
MAX
1160
0 to
c13
FREQUENCY (Hz)
AMPL
ITUD
E (d
Bc)
40k20k 60k 80k
fSAMPLE = 188kspsfIN = 25kHz
0
03
02
01
04
05
06
07
08
09
10
25 3530 40 45 50 55
OFFSET ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c14
VDD (V)
OFFS
ET E
RROR
(LS
B)
VREF = 2048V
0
03
02
01
04
05
06
07
08
09
10
-40 10-15 35 60 85
OFFSET ERROR vs TEMPERATURE
MAX
1160
0 to
c15
TEMPERATURE (degC)
OFFS
ET E
RROR
(LS
B)
VDD = 33VVREF = 2048V
-01
-007
-008
-009
-006
-005
-004
-003
-002
-001
0
25 3530 40 45 50 55
GAIN ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c16
VDD (V)
GAIN
ERR
OR (
LSB)
VREF = 2048V
Typical Operating Characteristics (continued)(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
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05
Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
MA
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16
00
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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05 SCL is high (Figure 5) A repeated START condition (Sr)
can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
MA
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
0980
0985
0990
0995
1000
1005
1010
1015
1020
-40 -15 10 35 60 85
INTERNAL 2048V REFERENCE VOLTAGE vs TEMPERATURE
MAX
1160
0 to
c10
TEMPERATURE (degC)
V REF
NOR
MAL
IZED
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
DIFFERENTIAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c11
DIGITAL OUTPUT CODE
DNL
(LSB
)
-05
-02
-03
-04
-01
0
01
02
03
04
05
0 10050 150 200 250 300
INTEGRAL NONLINEARITY vs DIGITAL CODE
MAX
1160
0 to
c12
DIGITAL OUTPUT CODE
INL
(LSB
)
-120
-80
-100
-40
-60
-20
0
0 100k
FFT PLOT
MAX
1160
0 to
c13
FREQUENCY (Hz)
AMPL
ITUD
E (d
Bc)
40k20k 60k 80k
fSAMPLE = 188kspsfIN = 25kHz
0
03
02
01
04
05
06
07
08
09
10
25 3530 40 45 50 55
OFFSET ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c14
VDD (V)
OFFS
ET E
RROR
(LS
B)
VREF = 2048V
0
03
02
01
04
05
06
07
08
09
10
-40 10-15 35 60 85
OFFSET ERROR vs TEMPERATURE
MAX
1160
0 to
c15
TEMPERATURE (degC)
OFFS
ET E
RROR
(LS
B)
VDD = 33VVREF = 2048V
-01
-007
-008
-009
-006
-005
-004
-003
-002
-001
0
25 3530 40 45 50 55
GAIN ERROR vs SUPPLY VOLTAGE
MAX
1160
0 to
c16
VDD (V)
GAIN
ERR
OR (
LSB)
VREF = 2048V
Typical Operating Characteristics (continued)(VDD = 33V (MAX11601MAX11603MAX11605) VDD = 5V (MAX11600MAX11602MAX11604) fSCL = 17MHz external clock (33 dutycycle) fSAMPLE = 188ksps single ended unipolar TA = +25degC unless otherwise noted)
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Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
MA
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05 SCL is high (Figure 5) A repeated START condition (Sr)
can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
MA
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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Detailed DescriptionThe MAX11600ndashMAX11605 ADCs use successive-approximation conversion techniques and input TH cir-cuitry to capture and convert an analog signal to aserial 8-bit digital output The MAX11600MAX11601are 4-channel ADCs the MAX11602MAX11603 are 8-channel ADCs and the MAX11604MAX11605 are 12-channel ADCs These devices feature a high-speed2-wire serial interface supporting data rates up to17MHz Figure 3 shows the simplified functional dia-gram for the MAX11604MAX11605
Power SupplyThe MAX11600ndashMAX11605 operate from a single supplyand consume 350microA at sampling rates up to 188kspsThe MAX11601MAX11603MAX11605 feature a 2048Vinternal reference and the MAX11600MAX11602MAX11604 feature a 4096V internal reference Alldevices can be configured for use with an external refer-ence from 1V to VDD
Analog Input and TrackHoldThe MAX11600ndashMAX11605 analog input architecturecontains an analog input multiplexer (MUX) a THcapacitor TH switches a comparator and a switchedcapacitor digital-to-analog converter (DAC) (Figure 4)
In single-ended mode the analog input multiplexer con-nects CTH to the analog input selected by CS[30] (seethe ConfigurationSetup Bytes (Write Cycle) section) The
charge on CTH is referenced to GND when converted Inpseudo-differential mode the analog input multiplexerconnects CTH to the positive analog input selected byCS[30] The charge on CTH is referenced to the nega-tive analog input when converted
The MAX11600ndashMAX11605 input configuration is pseudo-differential in that only the signal at the positiveanalog input is sampled with the TH circuitry The nega-tive analog input signal must remain stable within plusmn05 LSB (plusmn01 LSB for best results) with respect to GNDduring a conversion To accomplish this connect a01microF capacitor from the negative analog input to GNDSee the Single-EndedPseudo-Differential Input section
During the acquisition interval the TH switches are inthe track position and CTH charges to the analog inputsignal At the end of the acquisition interval the THswitches move to the hold position retaining the chargeon CTH as a sample of the input signal
During the conversion interval the switched capacitiveDAC adjusts to restore the comparator input voltage tozero within the limits of 8-bit resolution This actionrequires eight conversion clock cycles and is equiva-lent to transferring a charge of 18pF (VIN+ - VIN-)from CTH to the binary weighted capacitive DAC form-ing a digital representation of the analog input signal
Sufficiently low source impedance is required to ensurean accurate sample A source impedance below 15kΩdoes not significantly degrade sampling accuracy To
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
8 _______________________________________________________________________________________
PIN
MAX11600MAX11601
MAX11602MAX11603
MAX11604MAX11605
NAME FUNCTION
1 2 3 12 11 10 12 11 10 AIN 0 AIN 1 AIN 2
mdash 9ndash5 9ndash5 AIN3ndashAIN7
mdash mdash 4 3 2 AIN8ndashAIN10
Analog Inputs
4 mdash mdash AIN3REFAnalog Input 3Reference InputOutput Selected in the setup register(see Tables 1 and 6)
mdash 1 mdash REFReference InputOutput Selected in the setup register (see Tables 1and 6)
mdash mdash 1 AIN11REFAnalog Input 11Reference InputOutput Selected in the setupregister (see Tables 1 and 6)
5 13 13 SCL Clock Input
6 14 14 SDA Data InputOutput
7 15 15 GND Ground
8 16 16 VDD Positive Supply Bypass to GND with a 01microF capacitor
mdash 2 3 4 mdash NC No Connection
Pin Description
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
minimize sampling errors with higher source imped-ances connect a 100pF capacitor from the analoginput to GND This input capacitor forms an RC filterwith the source impedance limiting the analog inputbandwidth For larger source impedances use a bufferamplifier to maintain analog input signal integrity
When operating in internal clock mode the TH circuitryenters its tracking mode on the ninth falling clock edgeof the address byte (see the Slave Address section)The TH circuitry enters hold mode two internal clockcycles later A conversion or a series of conversions isthen internally clocked (eight clock cycles per conver-sion) and the MAX11600ndashMAX11605 hold SCL lowWhen operating in external clock mode the TH circuit-ry enters track mode on the seventh falling edge of avalid slave address byte Hold mode is then entered onthe falling edge of the eighth clock cycle The conver-sion is performed during the next eight clock cycles
The time required for the TH circuitry to acquire aninput signal is a function of input capacitance If theanalog input source impedance is high the acquisitiontime lengthens and more time must be allowedbetween conversions The acquisition time (tACQ) is theminimum time needed for the signal to be acquired It iscalculated by
tACQ ge 625 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedanceRIN = 25kΩ and CIN = 18pF tACQ is 1fSCL for externalclock mode For internal clock mode the acquisitiontime is two internal clock cycles To select RSOURCEallow 625ns for tACQ in internal clock mode to accountfor clock frequency variations
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
tHDSTA
tSUDAT
tHIGHtR tF
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
P S
tHDSTA
tSUDAT
tHIGHtFCL
tHDDAT tHDSTA
S Sr A
SCL
SDA
tSUSTAtLOW
tBUFtSUSTO
S
tRCL tRCL1
HS MODE FS MODE
a) FS-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMING tFDAtRDA
ttR tF
Figure 1 I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2 Load Circuit
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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Analog Input BandwidthThe MAX11600ndashMAX11605 feature input tracking cir-cuitry with a 2MHz small signal bandwidth The 2MHzinput bandwidth makes it possible to digitize high-speed transient events and measure periodic signalswith bandwidths exceeding the ADCrsquos sampling rate byusing undersampling techniques To avoid high-fre-quency signals being aliased into the frequency bandof interest anti-alias filtering is recommended
Analog Input Range and ProtectionInternal protection diodes clamp the analog input toVDD and GND These diodes allow the analog inputs toswing from (GND - 03V) to (VDD + 03V) without caus-ing damage to the device For accurate conversionsthe inputs must not go more than 50mV below GND orabove VDD If the analog input exceeds VDD by morethan 50mV the input current should be limited to 2mA
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
10 ______________________________________________________________________________________
ANALOGINPUTMUX
AIN1
AIN11REF
AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9
AIN10
AIN0
SCLSDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROLLOGIC
REFERENCE4096V (MAX11604)2048V (MAX11605)
INTERNALOSCILLATOR
OUTPUT SHIFTREGISTER AND12-BYTE RAM
THE MAX11600MAX11601MAX11604MAX11605 USE THE SAME PIN FOR AIN_ AND REF WHILE THE MAX11602MAX11603 USE DIFFERENT PINS SEE THE PIN DESCRIPTION SECTION
REF
TH 8-BITADC
VDD
GND
MAX11604MAX11605
Figure 3 MAX11604MAX11605 Simplified Functional Diagram
TRAC
K
HOLD
CTH
TRAC
K
HOLD
DIFF
EREN
TIAL
SING
LE E
NDED
AIN0
AIN1
AIN2
AIN3REF
GND
ANALOG INPUT MUX
CAPACITIVEDAC
REF
MAX11600MAX11601
Figure 4 Equivalent Input Circuit
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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16
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can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
MA
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00
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05
random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
MA
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
Single-EndedPseudo-Differential InputThe SGLDIF bit of the configuration byte configures theMAX11600ndashMAX11605 analog input circuitry for single-ended or pseudo-differential inputs (Table 2) In single-ended mode (SGLDIF = 1) the digital conversion resultsare the difference between the analog input selected byCS[30] and GND (Table 3) In pseudo-differential mode(SGLDIF = 0) the digital conversion results are the differ-ence between the positive and the negative analog inputsselected by CS[30] (Table 4) The negative analog inputsignal must remain stable within plusmn05 LSB (plusmn01 LSB forbest results) with respect to GND during a conversion
UnipolarBipolarWhen operating in pseudo-differential mode the BIPUNI bit of the setup byte (Table 1) selects unipolar orbipolar operation Unipolar mode sets the differentialanalog input range from zero to VREF A negative differ-ential analog input in unipolar mode causes the digitaloutput code to be zero Selecting bipolar mode sets thedifferential input range to plusmnVREF2 with respect to thenegative input The digital output code is binary inunipolar mode and tworsquos complement binary in bipolarmode (see the Transfer Functions section)
In single-ended mode the MAX11600ndashMAX11605always operate in unipolar mode regardless of theBIPUNI setting and the analog inputs are internally ref-erenced to GND with a full-scale input range from zeroto VREF
Digital InterfaceThe MAX11600ndashMAX11605 feature a 2-wire interfaceconsisting of a serial-data line (SDA) and a serial-clockline (SCL) SDA and SCL facilitate bidirectional communi-cation between the MAX11600ndashMAX11605 and the mas-ter at rates up to 17MHz The MAX11600ndashMAX11605 areslaves that transmit and receive data The master (typical-ly a microcontroller) initiates data transfer on the bus andgenerates SCL to permit that transfer
SDA and SCL must be pulled high This is typicallydone with pullup resistors (500Ω or greater) (seeTypical Operating Circuit) Series resistors (RS) areoptional They protect the input architecture of theMAX11600ndashMAX11605 from high-voltage spikes on thebus lines and minimize crosstalk and undershoot of thebus signals
Bit TransferOne data bit is transferred during each SCL clockcycle Nine clock cycles are required to transfer thedata in or out of the MAX11600ndashMAX11605 The dataon SDA must remain stable during the high period ofthe SCL clock pulse Changes in SDA while SCL is highare control signals (see the START and STOPConditions section) Both SDA and SCL idle high whenthe bus is not busy
START and STOP ConditionsThe master initiates a transmission with a START condi-tion (S) a high-to-low transition on SDA with SCL highThe master terminates a transmission with a STOP condition (P) a low-to-high transition on SDA while
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 11
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SEL2 SEL1 SEL0 CLK BIPUNI RST X
BIT NAME DESCRIPTION
7 REG Register bit 1 = setup byte 0 = configuration byte (Table 2)
6 SEL2
5 SEL1
4 SEL0
Three bits select the reference voltage and the state of AIN_REF(MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) (Table 6)Default to 000 at power-up
3 CLK 1 = external clock 0 = internal clock Defaulted to zero at power-up
2 BIPUNI 1 = bipolar 0 = unipolar Defaulted to zero at power-up (see the UnipolarBipolar section)
1 RST 1 = no action 0 = resets the configuration register to default Setup register remains unchanged
0 X Donrsquot care can be set to 1 or 0
Table 1 Setup Byte Format
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can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
MA
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05 SCL is high (Figure 5) A repeated START condition (Sr)
can be used in place of a STOP condition to leave thebus active and in its current timing mode (see the HSMode section)
Acknowledge BitsSuccessful data transfers are acknowledged with anacknowledge bit (A) or a not-acknowledge bit (A) Boththe master and the MAX11600ndashMAX11605 (slave) gener-ate acknowledge bits To generate an acknowledge bitthe receiving device must pull SDA low before the risingedge of the acknowledge-related clock pulse (ninthpulse) and keep it low during the high period of the clockpulse (Figure 6) To generate a not acknowledge bit thereceiver allows SDA to be pulled high before the risingedge of the acknowledge-related clock pulse and leavesit high during the high period of the clock pulse
Monitoring the acknowledge bits allows for detection ofunsuccessful data transfers An unsuccessful datatransfer happens if a receiving device is busy or if asystem fault has occurred In the event of an unsuc-cessful data transfer the bus master should reattemptcommunication at a later time
Slave AddressA bus master initiates communication with a slavedevice by issuing a START condition followed by aslave address When idle the MAX11600ndashMAX11605continuously wait for a START condition followed bytheir slave address When the MAX11600ndashMAX11605recognize their slave address they are ready to acceptor send data The slave address has been factory pro-grammed and is always 1100100 for the MAX11600MAX11601 1101101 for MAX11602MAX11603 and1100101 for MAX11604MAX11605 (Figure 7) The leastsignificant bit (LSB) of the address byte (RW) deter-mines whether the master is writing to or reading fromthe MAX11600ndashMAX11605 (RW = zero selects a writecondition RW = 1 selects a read condition) Afterreceiving the address the MAX11600ndashMAX11605(slave) issue an acknowledge by pulling SDA low forone clock cycle
Bus TimingAt power-up the MAX11600ndashMAX11605 bus timingdefaults to fast mode (FS mode) allowing conversionrates up to 44ksps The MAX11600ndashMAX11605 mustoperate in high-speed mode (HS mode) to achieveconversion rates up to 188ksps Figure 1 shows the bustiming for the MAX11600ndashMAX11605 2-wire interface
HS ModeAt power-up the MAX11600ndashMAX11605 bus timing isset for FS mode The master selects HS mode by
addressing all devices on the bus with the HS modemaster code 0000 1XXX (X = donrsquot care) After success-fully receiving the HS-mode master code theMAX11600ndashMAX11605 issues a not acknowledgeallowing SDA to be pulled high for one clock cycle(Figure 8) After the not acknowledge theMAX11600ndashMAX11605 are in HS mode The master mustthen send a repeated START followed by a slaveaddress to initiate HS mode communication If the mas-ter generates a STOP condition the MAX11600ndashMAX11605 return to FS mode
ConfigurationSetup Bytes (Write Cycle)Write cycles begin with the master issuing a STARTcondition followed by 7 address bits (Figure 7) and 1write bit (RW = zero) If the address byte is successful-ly received the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then writes to the slave Theslave recognizes the received byte as the setup byte(Table 1) if the most significant bit (MSB) is 1 If theMSB is zero the slave recognizes that byte as the con-figuration byte (Table 2) The master can write either 1or 2 bytes to the slave in any order (setup byte thenconfiguration byte configuration byte then setup bytesetup byte only configuration byte only Figure 9) If theslave receives bytes successfully it issues an acknowl-edge The master ends the write cycle by issuing aSTOP condition or a repeated START condition Whenoperating in HS mode a STOP condition returns thebus to FS mode (see the HS Mode section)
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
12 ______________________________________________________________________________________
SCL
SDA
S PSr
Figure 5 START and STOP Conditions
SCL
SDA
S NOT ACKNOWLEDGE
ACKNOWLEDGE
1 2 8 9
Figure 6 Acknowledge Bits
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
MA
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05
Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
Data Byte (Read Cycle)A read cycle must be initiated to obtain conversionresults Read cycles begin with the bus master issuinga START condition followed by 7 address bits and aread bit (RW = 1) If the address byte is successfullyreceived the MAX11600ndashMAX11605 (slave) issue anacknowledge The master then reads from the slaveAfter the master has received the results it can issuean acknowledge if it wants to continue reading or a notacknowledge if it no longer wishes to read If theMAX11600ndashMAX11605 receive a not acknowledgethey release SDA allowing the master to generate aSTOP or repeated START See the Clock Mode andScan Mode sections for detailed information on howdata is obtained and converted
Clock ModeThe clock mode determines the conversion clock theacquisition time and the conversion time The clockmode also affects the scan mode The state of thesetup bytersquos CLK bit determines the clock mode (Table1) At power-up the MAX11600ndashMAX11605 default tointernal clock mode (CLK = zero)
Internal ClockWhen configured for internal clock mode (CLK = zero)the MAX11600ndashMAX11605 use their internal oscillatoras the conversion clock In internal clock mode theMAX11600ndashMAX11605 begin tracking analog input onthe ninth falling clock edge of a valid slave addressbyte Two internal clock cycles later the analog signalis acquired and the conversion begins While trackingand converting the analog input signal theMAX11600ndashMAX11605 hold SCL low (clock stretching)After the conversion completes the results are stored in
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 13
1 1 0 10 0 0 RW A
SLAVE ADDRESS
S
SCL
SDA
1 2 3 4 5 6 7 8 9
DEVICE SLAVE ADDRESS
1100100
1101101
MAX11600MAX11601
MAX11602MAX11603
1100101MAX11604MAX11605
Figure 7 Slave Address Byte
0 0 0 10 X X X A
HS MODE MASTER CODE
SCL
SDA
S Sr
FS MODE HS MODE
Figure 8 FS Mode to HS Mode Transfer
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
MA
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
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random access memory (RAM) If the scan mode is setfor multiple conversions they all happen in successionwith each additional result being stored in RAM TheMAX11600MAX11601 contain 8 bytes of RAM theMAX11602MAX11603 contain 8 bytes of RAM and theMAX11604MAX11605 contain 12 bytes of RAM Onceall conversions are complete the MAX11600ndashMAX11605 release SCL allowing it to be pulled highThe master can now clock the results out of the outputshift register at a clock rate of up to 17MHz SCL isstretched for a maximum acquisition and conversiontime of 76micros per channel (Figure 10)
The device RAM contains all of the conversion resultswhen the MAX11600ndashMAX11605 release SCL The con-verted results are read back in a first-in-first-out (FIFO)sequence If AIN_REF is set to be a reference input oroutput (SEL1 = 1 Table 6) AIN_REF is excluded froma multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF RAM contents can be read continu-ously If reading continues past the last result stored inRAM the pointer wraps around and points to the firstresult Note that only the current conversion results areread from memory The device must be addressed witha read command to obtain new conversion results
The internal clock modersquos clock stretching quiets theSCL bus signal reducing the system noise during con-version Using the internal clock also frees the master(typically a microcontroller) from the burden of runningthe conversion clock
External ClockWhen configured for external clock mode (CLK = 1)the MAX11600ndashMAX11605 use SCL as the conversionclock In external clock mode the MAX11600ndashMAX11605 begin tracking the analog input on the sev-enth falling clock edge of a valid slave address byteOne SCL clock cycle later the analog signal isacquired and the conversion begins Unlike internalclock mode converted data is available immediatelyafter the slave-address acknowledge bit The devicecontinuously converts input channels dictated by thescan mode until given a not acknowledge There is noneed to re-address the device with a read command toobtain new conversion results (Figure 11)
The conversion must complete in 9ms or droop on theTH capacitor degrades conversion results Use internalclock mode if the SCL clock period exceeds 1ms
The MAX11600ndashMAX11605 must operate in externalclock mode for conversion rates up to 188ksps
Scan ModeSCAN0 and SCAN1 of the configuration byte set thescan-mode configuration Table 5 shows the scanningconfigurations If AIN_REF is set to be a reference inputor output (SEL1 = 1 Table 6) AIN_REF is excludedfrom a multichannel scan This does not apply to theMAX11602MAX11603 as each provides separate pinsfor AIN7 and REF
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
14 ______________________________________________________________________________________
B 2-BYTE WRITE CYCLE
SLAVE TO MASTER
MASTER TO SLAVE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
S
1
SLAVE ADDRESS A
7 1 1
W SETUP ORCONFIGURATION BYTE
8
P OR Sr
1
A
1
MSB DETERMINES WHETHERSETUP OR CONFIGURATION BYTE
A
1 8
A 1-BYTE WRITE CYCLE
NUMBER OF BITS
NUMBER OF BITS
Figure 9 Write Cycle
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
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00
ndashMA
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05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
MA
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Applications InformationPower-On Reset
The configuration and setup registers (Tables 1 and 2)default to a single-ended unipolar single-channel con-version on AIN0 using the internal clock with VDD as thereference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) configured as an analog inputFor the MAX11602MAX11603 the REF pin is floatingafter power-up The RAM contents are unknown afterpower-up
Automatic ShutdownSEL[20] of the setup byte (Tables 1 and 6) controls thestate of the reference and AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) If automatic shutdown is selected (SEL[20] =100) shutdown occurs between conversions when theMAX11600ndashMAX11605 are idle When operating in exter-nal clock mode a STOP condition must be issued to placethe devices in idle mode and benefit from automatic shut-down A STOP condition is not necessary in internal clockmode to benefit from automatic shutdown because power-down occurs once all contents are written to memory(Figure 10) All analog circuitry is inactive in shutdown andsupply current is less than 1microA The digital conversionresults are maintained in RAM during shutdown and areavailable for access through the serial interface at anytime prior to a STOP or repeated START condition
When idle the MAX11600ndashMAX11605 wait for a STARTcondition followed by their slave address (see theSlave Address section) Upon reading a valid addressbyte the MAX11600ndashMAX11605 power up The analogcircuits do not require any wakeup time from shutdownwhether using external or internal reference
Automatic shutdown results in dramatic power savingsparticularly at slow conversion rates For example at aconversion rate of 10ksps the average supply currentfor the MAX1036 is 8microA and drops to 2microA at 1ksps At 01ksps the average supply current is just 1microA (seeAverage Supply Current vs Conversion Rate in theTypical Operating Characteristics section)
Reference VoltageSEL[20] of the setup byte (Table 1) controls the refer-ence and the AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)configuration (Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) is configured to bea reference input or reference output (SEL1 = 1) con-versions on AIN_REF appear as if AIN_REF is con-nected to GND (see note 2 of Tables 3 and 4)
Internal ReferenceThe internal reference is 4096V for the MAX11600MAX11602MAX11604 and 2048V for the MAX11601MAX11603MAX11605 SEL1 of the setup byte controlswhether AIN_REF (MAX11600MAX11601MAX11604MAX11605) is used for an analog input or a reference(Table 6) When AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603) isconfigured to be an internal reference output (SEL[21] =11) decouple AIN_REF (MAX11600MAX11601MAX11604MAX11605) or REF (MAX11602MAX11603)to GND with a 001microF capacitor Due to the decouplingcapacitor and the 675Ω reference source impedanceallow 80micros for the reference to stabilize during initialpower-up Once powered up the reference alwaysremains on until reconfigured The reference should notbe used to supply current for external circuitry When theMAX11602MAX11603 is in shutdown the internal refer-ence output is in a high-impedance state
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 15
BIT 7(MSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0(LSB)
REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGLDIF
BIT NAME DESCRIPTION7 REG Register bit 1 = setup byte (Table 1) 0 = configuration byte6 SCAN15 SCAN0
Scan select bits Two bits select the scanning configuration (Table 5) Default to 00 atpower-up
4 CS33 CS22 CS11 CS0
Channel select bits Four bits select which analog input channels are to be used for conversion(Tables 3 and 4) Default to 0000 at power-up For the MAX11600MAX11601 CS3 and CS2 areinternally set to 0 For the MAX11602MAX11603 CS3 is internally set to zero
0 SGLDIF1 = single-ended 0 = pseudo-differential (Tables 3 and 4) Default to 1 at power-up (see theSingle-EndedPseudo-Differential Input section)
Table 2 Configuration Byte Format
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
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External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
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00
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05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
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00
ndashMA
X1
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05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
B SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE tACQ + tCONV le 76micros PER CHANNEL
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
18
RESULT A
1
A SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCHA
NUMBER OF BITS
P OR Sr
18
RESULT 1 A
1
A
8
RESULT 2 A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
tCONV1
CLOCK STRETCH
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
11
Figure 10 Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
tCONV1
tACQ1tCONV2
tACQ2tCONVN
tACQN
tCONVtACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
7 1 1
R
S
1
A
7 1 1
R P OR Sr
18
A
1
A
8
A
8
B SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11 External Clock Mode Read Cycles
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
16 ______________________________________________________________________________________
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
MA
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05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
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27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
MA
X1
16
00
ndashMA
X1
16
05
External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
1 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero2 When SEL1 = 1 a single-ended read of AIN3REF (MAX11600MAX11601) or AIN11REF (MAX11604MAX11605) returns GND This
does not apply to the MAX11602MAX11603 as each provides separate pins for AIN7 and REF
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 17
CS31 CS21 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 2 GN D
0 0 0 0 + -
0 0 0 1 + -
0 0 1 0 + -
0 0 1 1 + -
0 1 0 0 + -
0 1 0 1 + -
0 1 1 0 + -
0 1 1 1 + -
1 0 0 0 + -
1 0 0 1 + -
1 0 1 0 + -
1 0 1 1 + -
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 3 Channel Selection in Single-Ended Mode (SGLDIF = 1)
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
MA
X1
16
00
ndashMA
X1
16
05
External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
18 ______________________________________________________________________________________
CS32 CS22 CS1 CS0 AIN0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 3
0 0 0 0 + -
0 0 0 1 - +
0 0 1 0 + -
0 0 1 1 - +
0 1 0 0 + -
0 1 0 1 - +
0 1 1 0 + -
0 1 1 1 - +
1 0 0 0 + -
1 0 0 1 - +
1 0 1 0 + -
1 0 1 1 - +
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Table 4 Channel Selection in Pseudo-Differential Mode (SGLDIF = 0)1
1 When scanning multiple channels (SCAN0 = 0) CS0 = 0 causes the even-numbered channel-select bits to be scanned while CS0 = 1causes the odd-numbered channel-select bits to be scanned For example if the MAX11604MAX11605 SCAN[10] = 00 and CS[30] =1010 a pseudo-differential read returns AIN0ndashAIN1 AIN2ndashAIN3 AIN4ndashAIN5 AIN6ndashAIN7 AIN8ndashAIN9 and AIN10ndashAIN11 If theMAX11604MAX11605 SCAN[10] = 00 and CS[30] = 1011 a pseudo-differential read returns AIN1ndashAIN0 AIN3ndashAIN2 AIN5ndashAIN4AIN7ndashAIN6 AIN9ndashAIN8 and AIN11ndashAIN10
2 For the MAX11600MAX11601 CS3 and CS2 are internally set to zero For the MAX11602MAX11603 CS3 is internally set to zero3 When SEL1 = 1 a pseudo-differential read between AIN2 and AIN3REF (MAX11600MAX11601) or AIN10 and AIN11REF
(MAX11604MAX11605) returns the difference between GND and AIN2 or AIN10 respectively For example a pseudo-differentialread of 1011 returns the negative difference between AIN10 and GND This does not apply to the MAX11602MAX11603 as each pro-vides separate pins for AIN7 and REF
MA
X1
16
00
ndashMA
X1
16
05
External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
MA
X1
16
00
ndashMA
X1
16
05
External ReferenceThe external reference can range from 10V to VDD Formaximum conversion accuracy the reference must beable to deliver up to 30microA and have an output impedanceof 1kΩ or less If the reference has a higher output imped-ance or is noisy bypass it to GND as close as possible toAIN_REF (MAX11600MAX11601MAX11604MAX11605)or REF (MAX11602MAX11603) with a 01microF capacitor
Transfer FunctionsOutput data coding for the MAX11600ndashMAX11605 isbinary in unipolar mode and tworsquos complement binary inbipolar mode with 1 LSB = VREF2N where N is the num-ber of bits (8) Code transitions occur halfway betweensuccessive-integer LSB values Figures 12 and 13 showthe inputoutput (IO) transfer functions for unipolar andbipolar operations respectively
SCAN1 SCAN0 SCANNING CONFIGURATION
0 0 Scans up from AIN0 to the input selected by CS3ndashCS0 (default setting)
0 1 Converts the input selected by CS3ndashCS0 eight times
MAX11600MAX11601 Scans upper half of channelsScans up from AIN2 to the input selected by CS1 and CS0 When CS1 and CS0 are set for AIN0 AIN1 andAIN2 the scanning stops at AIN2 (MAX11600MAX11601)
MAX11602MAX11603 Scans upper quartile of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11602MAX11603)
1 0
MAX11604MAX11605 Scans upper half of channelsScans up from AIN6 to the input selected by CS3ndashCS0 When CS3ndashCS0 is set for AIN0ndashAIN6 the scanningstops at AIN6 (MAX11604MAX11605)
1 1 Converts the channel selected by CS3ndashCS0
Table 5 Scanning Configuration
When operating in external clock mode there is no difference between SCAN[10] = 01 and SCAN[10] = 11 and converting continuesuntil a not acknowledge occurs
SEL2 SEL1 SEL0REFERENCE
VOLTAGE
AIN_REF(MAX11600MAX11601MAX11604MAX11605)
REF(MAX11602MAX11603)
INTERNALREFERENCE STATE
0 0 X VDD Analog input Not connected Always off
0 1 X External reference Reference input Reference input Always off
1 0 0 Internal reference Analog input Not connected AutoShutdown
1 0 1 Internal reference Analog input Not connected Always on
1 1 X Internal reference Reference output Reference output Always on
Table 6 Reference Voltage AIN_REF and REF Format
X = Donrsquot care
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 19
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
20 ______________________________________________________________________________________
Layout Grounding and BypassingFor best performance use PC boards Wire-wrap config-urations are not recommended since the layout shouldensure proper separation of analog and digital traces Donot run analog and digital lines parallel to each other anddo not lay out digital signal paths underneath the ADCpackage Use separate analog and digital PCB groundsections with only one star point (Figure 14) connectingthe two ground systems (analog and digital) For lowestnoise operation ensure the ground return to the stargroundrsquos power supply is low impedance and as short aspossible Route digital signals far away from sensitiveanalog and reference inputs
High-frequency noise in the power supply (VDD) couldinfluence the proper operation of the ADCrsquos fast comparator Bypass VDD to the star ground with a01microF capacitor located as close as possible to theMAX11600ndashMAX11605 power-supply pin Minimizecapacitor lead length for best supply-noise rejectionand add an attenuation resistor (5Ω) if the power sup-ply is extremely noisy
INPUT VOLTAGE (LSB)
OUTPUT CODE
111111101101
1100
0000000100100011
2 3
256VREF1 LSB =
1 253 255254
REF
2560 252
Figure 12 Unipolar Transfer Function
INPUT VOLTAGE (LSB)
OUTPUT CODE(TWOS COMPLEMENT)
011101100101
0100
1000100110101011
-1-126 -125
256VREF1 LSB =
0 +1-127 +125 +127+126
0000 0001
1111
REF
+128-128 +124
NEGATIVE INPUT
Figure 13 Bipolar Transfer Function
3V5V VLOGIC = 3V5V GND
SUPPLIES
DGND3V5VGND
01microF
VDD
DIGITALCIRCUITRYMAX11600ndash
MAX11605
R = 5Ω
OPTIONAL
Figure 14 Power-Supply and Grounding Connections
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
DefinitionsIntegral Nonlinearity
Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line Thisstraight line can be either a best-straight-line fit or a linedrawn between the end points of the transfer functiononce offset and gain errors have been nullified The INLis measured using the end point method
Differential NonlinearityDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB ADNL error specification of less than 1 LSB guaranteesno missing codes and a monotonic transfer function
Aperture JitterAperture jitter (tAJ) is the sample-to-sample variation inthe time between the samples
Aperture DelayAperture delay (tAD) is the time between the risingedge of the sampling clock and the instant when anactual sample is taken
Signal-to-Noise RatioFor a waveform perfectly reconstructed from digital sam-ples signal-to-noise ratio (SNR) is the ratio of full-scaleanalog input (RMS value) to the RMS quantization error(residual error) The ideal theoretical minimum analog-to-digital noise is caused by quantization error only andresults directly from the ADCrsquos resolution (N bits)
SNR = (602 N + 176)dB
In reality there are other noise sources besides quanti-zation noise including thermal noise reference noiseclock jitter etc Therefore SNR is computed by takingthe ratio of the RMS signal to the RMS noise whichincludes all spectral components minus the fundamen-tal the first five harmonics and the DC offset
Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of thefundamental input frequencyrsquos RMS amplitude to RMSequivalent of all other ADC output signals
SINAD (dB) = 20 log (SignalRMSNoiseRMS)
Effective Number of Bits Effective number of bits (ENOB) indicates the globalaccuracy of an ADC at a specific input frequency andsampling rate An ideal ADCrsquos error consists of quanti-zation noise only With an input range equal to theADCrsquos full-scale range calculate the ENOB as follows
ENOB = (SINAD - 176)602
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the RMSsum of the input signalrsquos first five harmonics to the fun-damental itself This is expressed as
where V1 is the fundamental amplitude and V2 throughV5 are the amplitudes of the 2nd- through 5th-orderharmonics
Spurious-Free Dynamic RangeSpurious-free dynamic range (SFDR) is the ratio of RMSamplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next-largest distortioncomponent
Chip InformationPROCESS BiCMOS
THD V V V V V= times + + +⎛⎝
⎞⎠
⎛
⎝⎜⎞
⎠⎟20 2
23
24
25
21log
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
______________________________________________________________________________________ 21
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
22 ______________________________________________________________________________________
SDA
SCLAIN3REF
1
2
8
7
VDD
GNDAIN1
AIN2
AIN0
SOT23
+
+
TOP VIEW
3
4
6
5
MAX11600MAX11601
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11REF VDD
GND
SDA
SCL
AIN0
AIN1
AIN2
AIN3
( ) INDICATES PINS ON THE MAX11602MAX11603
MAX11602ndashMAX11605
QSOP
(NC) AIN10
(NC) AIN9
AIN6
(NC) AIN8
AIN7
AIN5
AIN4
Pin Configurations
OPTIONAL
RS
RS
ANALOGINPUTS
microC SDA
SCL
GND
VDD
SDA
SCL
AIN0AIN1AIN2AIN3REF
5V
5V
RP
RP
5V
MAX11600ndashMAX11605
Typical Operating Circuit
Package InformationFor the latest package outline information and land patterns goto wwwmaxim-iccompackages
PACKAGE TYPE PACKAGE CODE DOCUMENT NO
8 SOT23 K8CN+2 21-0078
16 QSOP E16+4 21-0055
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
MA
X1
16
00
ndashMA
X1
16
05
27V to 36V and 45V to 55V Low-Power4-8-12-Channel 2-Wire Serial 8-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses areimplied Maxim reserves the right to change the circuitry and specifications without notice at any time
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408-737-7600 ____________________ 23
copy 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
Revision History
REVISIONNUMBER
REVISIONDATE
DESCRIPTIONPAGES
CHANGED
0 409 Introduction of the MAX11600MAX11601MAX11603 mdash
1 709 Introduction of the MAX11602MAX11604MAX11605 1
2 310 Changed top mark on the MAX11600MAX11601 1
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T
Mouser Electronics
Authorized Distributor
Click to View Pricing Inventory Delivery amp Lifecycle Information Maxim Integrated
MAX11600EKA+T MAX11601EKA+T MAX11602EEE+ MAX11603EEE+ MAX11604EEE+ MAX11605EEE+
MAX11602EEE+T MAX11603EEE+T MAX11604EEE+T MAX11605EEE+T