Post on 11-Jan-2016
1
Low Drop-Out Voltage RegulatorsLow Drop-Out Voltage Regulators
ECEN 607(ESS)
Analog and Mixed-Signal Center, Texas A&M University
2
Power Management• Why do we need power management?
– Batteries discharge “almost” linearly with time.– Circuits with reduced power supply that are time dependent
operate poorly. Optimal circuit performance can not be obtained.– Mobile applications impose saving power as much as possible.
Thus, the sleep-mode and full-power mode must be carefully controlled.
– What is the objective of a power converter?• To provide a regulated output voltage
Voltage
Battery (i.e. Li-ion)
Regulated Voltage
Time
3
What are the conventional power converters?– Low drop-out linear regulator (LDO)
– Switch-inductor regulator (switching regulators)
– Switch-capacitor regulator (charge pump)
Why do we need different Power Converters Types?– Different applications
– Desired efficiency and output ripple
What is the purpose of combining several converters?
CP LDOBattery+
-VREGULATED
LDO CPBattery+
-VREGULATED
SR LDOBattery+
-VREGULATED
Can we combine them?
4
Linear Regulator: Principles
Thus in order to keep constant Vo, the value of the controlling resistor
RC yields:
How can we automatically pick the value of RC such that Vo= Vdesired, reg-voltage?
VBAT
RC
RLOAD VO
+
-
O
LDO
LOAD
O
OBAT
LOAD
O
BAT
LOADC V
VR
V
VVR
V
VRR 1
– Vo must be constant and
– VBAT is changing as a function of time
BATCLOAD
LOADO V
RR
RV
LOADCRR
FeedbackControl
RLOAD
RC
VC
VBATVO
+
-
5
How can we implement RC and the Feedback Control?
Can we implement RC as follows? For which applications?
a ba b
VC = VGS
NMOS Transistor
ILOAD
Vdo = ILOADRC
a b
VC = -VGS = VSG
PMOS Transistor
VDO,n= VSAT+VgsVDO,p= VSD(SAT)
RC1 RC2
a b
MNVC
a bRC1 RC2
MP VC
MN and MP are transistors operating in the Ohmic region. Discuss the option.
ID
VGS
6
How the feedback control could be implemented?
• Remarks– Make sure the closed loop is negative
– For an ideal op amp gain, the differential input is zero, i.e.
– VREF is a Bandgap voltage which is also supplied by VBAT=VIN.
Error Amplifier
VC,PMOS
R1
R2
VREF
VO
Error Amplifier
VC,NMOS
R1
R2
VREF
VO
021
2 REFO
VRR
RV REFOREGUTO
VR
RVVV
2
11OR
7
The efficiency is defined as:
• Where VDO is the voltage drop across the pass transistor, i.e. VDS
• The output error voltage (EVO) is defined as:
IN
DOIN
IN
OUT
LOADIN
LOADOUT
IN
OUT
V
VV
V
V
IV
IV
P
P
BAT
DO
V
V1
%100
LOADC
C
VO RR
RE
%100
MAXOUT
LOADOUTMAXOUT
VO V
VVE
OR
8
• Let us analyze the basic LDO architecture. First, we will consider ideal components, then the non-idealities are introduced together with the accompanied design challenges to tackle
LDO Analysis
VIN = VBAT
Basic LDO Topology
REFEAmEAmDIVm
op
IN
Lop
O VAgAgR
Vgr
VRRr
V
11
11111
Small Signal Representation
011
121
R
V
RRV O
DIV
(1)
(2)
VoVINAEA( VDIV - VREF)
VX
VDIV
R2
R1
rop
RL
gm( Vx – ViN )
VIN
Error Amplifier
RefPMOS Pass Transistor
R1
R2
Io
Load (RL)
AEA
VDIV
9
]1[
)1(
L
opEAPT
EAPTREFPTino
R
rAA
AAVAVV
Where: LopmPT RRRRRRrgA )( and ,)/( , 21212
Thus Vo can be expressed as:
)1()1( EAPT
EAPTREF
EAPT
PTino AA
AAV
AA
AVV
If EAPT AAT Vo yields:)1()1(
/
T
TV
T
ATVV REFEAin
o
T is the open loop gain. Furthermore for T >>1
REF
EA
ino
V
A
VV
Observe that Vin is attenuated by AEA and Vref is not.
Solving the (1) and (2), Vo becomes:
10
EAPT
PT
EAPT
PT
in
oR AA
A
AA
A
V
VL
1)1(
EAin
o
R AV
VL
1
refV
in
osREF
EAin
o
V
VV
R
R
AV
V
2
111
osV
The line regulation is a steady-state specification. It can be defined as:
For a practical case with non-idealities such as offset Op-Amp voltage
and reference voltage error i.e. ; the line regulator becomes:
Observe that designers should also minimize:
and provide Vref to be independent of VBAT and temperature and process variations.
Line Regulation
osV
11
o
oBATLoad
o
DSLoad
OUT
DSC V
VVR
V
VR
I
VR
oDCDSin IIVVV
Note that Rc given in page 3 for a transistor can be expressed as:
In order to maintain the regulation the transistor must operate properly
NMOS case
Exercise: Repeat the above case for a PMOS case
12
Load/Line Regulation
Let us assume the error amplifier is a transconductance amplifier of value GEA and α is the current gain of the pass transistor i.e.
Loeqoo RRRIRIV //)( 21
Loo RIV
oEAeqDIVEAo VRRRGRVGI )/( 212
Thus
Furthermore:
Then, the load regulation can be expressed as:
11
2
1
R
R
GI
V
EAo
o
Or line regulation:
LDSEAin
o
RRR
R
GV
V
1
11
2
1
Io
RL
Vin Vo+∆Vo
R1
R2
∆VDIV
VREF
GEARL
13
Efficiency Calculation
%7010071.4)100150(
3.3150
AmA
mA
max,,max
,max
)( inqoo
alminnoouto
VII
VI
Example of efficiency: A 3.3V LDO with 3.7 V < Vin < 4.71V, 100mA < Io < 150mA
Io,q (maximum quiescent current) = 100 μA
The output current can be represented as a pulse for simulation purposes
Io,max
Io,min
t0 t1
Io,max
Io,min
t0 t4t1 t3
OR
14
LDO ESR Stability
One of the most challenging problems in designing LDO is the stability problems due to the closed loop and the parasitic components associated with the pass transistor and the error amplifier. In fact to compensate the loop stability a large external capacitor is often connected at the output. i.e.
Where CL is of the order of μF with a small equivalent series resistor (RESR).
Re-L
ImL
LC sC
ssZ
L
/1)(
LESRL CR/1
RESR
CL
Vo
15
LDO Parameters 1• Dropout voltage (Vdo); This is the difference between the minimumvoltage the input DC supply can attain and the regulated outputvoltage.• Input rail range; This is the input supply voltage range that can beregulated. The lower limit is dependent on the dropout voltage andupper limit on the process capability.• Output current range; This is the output current handling capabilityof the regulated output voltage. The minimum current limit is mainlydependent on the stability requirements and the maximum limitdependent on Safe Operating Area (SOA) of pass FET and alsomaintaining output voltage in regulation.• Output capacitor range; This is the specified output capacitance theregulator is expected to accommodate without going unstable for agiven load current range.• Output regulated voltage range; This is the output voltage variationthe regulator guarantees. When output voltage is in this range, it issaid to be in regulation.• Load regulation; This is the variation in output voltage as current moves from min to
max
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• Line regulation; This the variation in output voltage as supply• voltage is varied from minimum to maximum.• PSR; Power Supply Rejection ( or ripple rejection) is a measure of the• ac coupling between the input supply voltage on the output voltage.• Load/Line transient regulation; This is a measure of the response speed• of the regulator when subjected to a fast load/Vsupply change.• Short circuit current limit; This is the current drawn when the• output voltage is short circuited to ground. The lower limit is• determined by the maximum regulated load current and the upper• limit is mainly determined by the SOA and specified requirements• Power Efficiency; This is the ratio of the output load power• consumption to input supply power. Linear regulators are not really• efficient especially at high input supply voltages.• Overshoot: It is important to minimized high transient voltages at start-up
and during load and line transients.• Thermal Shut down: This is needed to protect the part from damage
LDO Parameters 2
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Conventional LDO: Modeling
Open Loop Block Diagram
Open Loop Transfer Function: 4321 HHHHTF
113
2
sCACR
RgH
GDVGSA
Am
13
sCRR
RsCRRgH
LESRPAR
PARLESRPARmp
12
24 RR
RH
11
1
sCR
RgH
pp
pm
LdsPAR RRRRR 21 ds
ds IR
1
Note: The error amplifier is a two-stage amplifier without miller compensation
Close Loop Schematic
parmpv RgA
mVVmVV DSSATPassdropout 200200
2
2 2
2
1
DSSATPassoxp
DDSSATPassoxpD
VC
I
L
WV
L
WCI
Loop Breaking Point for Stability Analysis
R1
R2
RL
RESR
CL
VREF
Rds
1EH1EF
Error Amplifier
VIN
Vout
PND1
PD
PND2
z
CGD
CGs
A D
C
VTest
B
loadoxpmpi
L
WCg
2
VDSSATPass : Vdsat of the pass transistor
RPAR : Output impedance
RDS : Drain to source impedance of the pass transistor
RL : Load resistance
R1 &R2 : Feedback Resistors
Vdropout : Minimum voltage drop across the input and output terminalsof the LDO with shich the system is able to regulate.
18
Error Amplifier AEA
1. CGATE is connected to output node.
2. Miller Compensation is not required since the dominant pole is at the output.
Notes:
Two stage amplifier without miller compensation
outmmoRgRgA
8011
Dominant pole
Cgate
01R
OUTR
gate
mom
C
gRgGBW 811
19
Matlab/Simulink Macromodel Pass Transistor Transconductance
Error Amplifier Nondominant Pole
Dominant Pole / Compensation Zero
Non-dominat Pole due to Pass Transistor Gate Capacitance
Feedback Factor
21
2
RR
RK
FC
o10
5esrr
KR 4201
KR 2402
mVVdsat 200
mAiload 50
1.0
pFCgd 30
pFCgs 50
MRa 36.7
VmAGm /35.13
VAGm /62.151
kRp 64
fFC p 100
load
DS iR
1
load
outL i
VR
VVout 3.3
loadmpi
e
eeg
66.0
344680
Formulas and Component Values
20
Fu ~ 2.7MHz
PM ~ 90°
Loop Gain ~ 100dB
Phase boost due to Compensation Zero
ESRL
RCZ
1
Loop Gain and Phase
Simulation Results From Simulink
DP
z
1NDP
2NDP
21
Notes:1-Open Loop System2- Load Variation (iload varies from 10mA to 50mA)3- The load variation (iload) was simulated in Matlab using a “for loop”
Open Loop Gain and Phase Under Load Variation
22
Simulation Results From Matlab
Step Response
Vout varies from 0 to 3.3V
Vin varies from 0 to 3.5V
23
Power Supply Rejection
Problem:
Low frequency and high frequency noise affects the operation of the highly sensitive circuits
External noise is mainly coupled through the supply lines
A regulator (LDO) is mandatory with high PSR
Vsupply
24
Current Solutions:
RC filtering: Larger drop-out voltage, and larger power consumption
Cascading of LDO: Larger area, power consumption, larger drop-out voltage
Combined RC filtering and cascading: Larger area and power consumption, larger drop-out voltage and complexity
Power Supply Rejection Existing Solutions VIN VDDVIN
VIN VIN
25
Enhancing PSR over a wide frequency range
• The NMOS cascode, MNC, shields the entire regulator from fluctuations in the power supply.
• MNC gate needs to be biased at a voltage above the supply using a charge pump.
• MNC acts as a voltage follower for noise at its gate, it is critical to shield the gate of MNC from supply fluctuations using an RC filter to shunt supply ripple to ground.
G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance ,” ISSCC, feb. 2007.
Proposed Topology
26
Enhancing PSR over a wide frequency range
• With the help of an NMOS cascode, a charge pump, a voltage reference and an RC filter to shield the entire regulator from power supply fluctuations, a 5mA LDO regulator utilizing 60pF of on-chip capacitance achieves a worst-case PSR performance of -27dB over 50MHz.
G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance ,” ISSCC, feb. 2007.
27
Stability and PSR Simulations
• Stability test (Open Loop)
AC signal is injected here
Frequency Response
Fu ~ 10MHz PM ~ 60°Loop Gain ~ 65dB
Open loop gain shows a low pass frequency response
28
Stability and PSR Simulations (Continue)
• PSR simulation
AC signal is injected here PSR versus Frequency
PSR curve shows a Quasi-Band Pass frequency response it is less than -40 dB up to 10KHz, -30 dB at 100 KHz
29
• Internal zero generation using a differentiator– An auxiliary fast loop (differentiator) provides both a fast transient detector path
as well as internal ac compensation. – The simplest coupling network might be a unity gain current buffer.
– Cf senses the changes in the output voltage in the form of a current that is then injected into pass transistor gate capacitance.
Different Compensation Techniques for Stability Purposes
Different Compensation Techniques for Stability Purposes
Robert J. Milliken, Jose Silva-Martínez, and Edgar Sánchez-Sinencio “Full on-chip CMOS low-dropout voltage regulator,” IEEE Trans. on Circuits and Systems – I, pp 1879-1890, vol. 54, Issue 9, Sept. 2007.
30
• Capacitive feedback for frequency compensation – It introduces a left hand plane zero in the feedback loop to replace the zero generated
by ESR of the output capacitor. – the capacitor is split into two frequency-dependent voltage-controlled current sources
(VCCS) and grounded capacitors.– Instead of adding a pole–zero pair with zero at lower frequency than the pole, in this
technique only a zero is added. – It needs a frequency dependent voltage control current source (VCCS).
Different Compensation Techniques
Chaitanya K. Chava, and Jose Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 1041-1050, June 2004.
31
Different Compensation Techniques
• DFC frequency compensation – It is a pole-splitting compensation technique especially designed for compensating
amplifier with large-capacitive load.
– DFC block composed of a negative gain stage with a compensation capacitor Cm2, and it is connected at output of the first stage. Another compensation capacitor Cm1 is required to achieve pole-splitting effect.
– The feedback-resistive network creates a medium frequency zero for improving the LDO stability.
K. N. Leung, and P.K.T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol.38, no.10, pp.1691-1702, Oct. 2003.
32
• Pole-zero tracking frequency compensation– To have pole-zero cancellation, the position of the output pole po and compensation
zero zc should match each other.
– The resistor is implemented using a transistor Mc in the linear region, where its value is controlled by the gate terminal.
Different Compensation Techniques
K. C. Kwok, P. K. T. Mok. “Pole-zero tracking frequency compensation for low dropout regulator,” 2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735-738,May 2002.
33
Fast Transient Response • A current-efficient adaptively biased regulation scheme is implemented using a low-
voltage high-speed super current mirror. It does not require a compensation capacitor.
• The adaptively error amplifier drives a small transconductance (MA9) to modulate the output current IOUT through a transient-enhanced super current mirror.
Yat Lei Lam, Wing-Hung Ki, “A 0.9V 0.35µm Adaptively Biased CMOS LDO Regulator with Fast Transient Response,” 2008 IEEE International Solid-State Circuit Conference, February 2008.
34
Noise in Linear Regulators• LDO noise is sometimes confused with PSRR
PSRR is the amount of ripple on the output coming from the ripple of the input. On the other hand, noise is purely a physical phenomenon that occurs with the transistors and resistors
(ideally, capacitors are noise free) on a very fundamental level.
• Primary noise sources:1. Bandgap-Reference (Primary source of noise) Possible solution: add a low-pass filter (LPF) to the output of the bandgap.
– Drawback: it can slow down the output startup.
2. The resistor divider ( thermal noise = 4KTR ) Possible solution: Use resistors as small as possible.
– Drawback: Smaller resistors burn more current through the feedback divider. Possible solution: add a capacitor across the top resistor in the resistor feedback divider. At high
frequencies it reduces the close loop gain and thus the noise.– Drawback: it could slow down start-up time significantly, since the capacitor would have to be
charged by the current in the resistor divider.
3. Input stage of the error amplifier (thermal and flicker noise) Possible Solution: Large input drivers.
– Drawback: larger area.
• Second order noise sources:– Load current and output capacitance (Phase Margin)
• Low phase margin will cause peaking in the close-loop gain and since the close-loop gain amplifies this noise, the total output noise increases.
Reference: J. C. Teel, “Understanding noise in linear regulators” Analog Application Journal, 2Q 2005, www.ti.com/aaj
35
LDO Design Example
Parameters Specifications
VIN 3.5V
VOUT 3.3V
ILoad 0mA-50mA
IQ < 100µA
Technology 0.5µm CMOS
R2
R1
RL
RESR
CL
Error Amplifier
VREF
Pass Transistor
VOUT
Conventional LDO
36
Vin Vout ILoad
VdropoutRL
W/L
CGate Cp RpRDS
Adjust poles and zeros locations using CL and RESR
Check stability
Design Error Amplifier
Calculate non dominant poles: PND1, PND2
Check transient, PSR, load regulation, line regulation, …
Design Flow Diagram
RA
37
LDO Design Example
mVVmVV DSSATPassdropout 200200
2
2 2
2
1
DSSATPassoxp
DDSSATPassoxpD
VC
I
L
WV
L
WCI
µPCox= 65µA/V2
Since
the pass transistor size can be calculated by:Assuming
462,38L
W
In order to minimize the gate capacitance, we use minimum length L = 0.6µm
mmmW 236.038462
oxGSCLWC
3
2oxDDG
CLWC where LdsPAR RRRRR 21 ds
ds IR
1
The gate capacitance of the pass transistor is given by the following equation:
GDparmpGSgate
CRgCC 1
38
The values of CGS and CGD can be also obtained if we run a dc simulation and verify the operating point of the pass transistor. Using the last method, we found:
REFOUTV
R
RV
1
21
Assuming a reference voltage of 1.2V and choosing R1 = 240K, We found R2 = 420K .
pFCGS
26 pFCDG
6.7
R1 and R2 are calculated using :
151
ds
DS gR
6650
3.3
mA
V
I
VR
LOAD
OUT
L
2/5035066.0
32361302 VmAe
e
eei
L
WCG
loadoxpmp
pFCRgCCGDparmpGSgate
5.361
126624042015 KKRPAR
Design Example (Continue)
39
Design Example (Continue)
The error amplifier is implemented using a two stage without miller compensation topology in order to achieve a gain larger than 60dB and GBW =7MHz using 0.5µm CMOS technology
– High DC Gain to guarantee high loop gain over the range of loads (AV > 60dB)
– Low output impedance for higher frequency pole created with CGS of pass transistor
– Internal poles must be kept at high frequencies, preferably > fU of the system (~1MHz)
– Low DC current consumption
– Low Noise
Error Amplifier schematic
Error Amplifier Design and Considerations
40
Design Example (Continue)
Magnitude Plot Phase Plot
Error Amplifier Simulation Results
Note: This results were obtained using Cgate = 36.5pF as the load
dBAo
65 MHzGBW 6.7 51PM
41
Design Example (Continue)
KHzCRR
PLESRPAR
D2.1
2
1
KHzCR
ZLESR
2.31 KHz
CRP
GateA
ND3.5
11
MHzCR
Ppp
ND3.7
12
Dominant Pole Location
First non-dominant pole location
Second non-dominant pole location
Zero location
Pole / Zero Locations
Notes: 1- RA was obtained from simulations. Basically, it is the output resistance of the error amplifier. 2-PND2 is greater than 7.3MHz since the phase margin of the amplifier is around 51°. This is good news since we want this pole to be located above the gain bandwidth product of the overall system. 3- RESR equal 5 was chosen for stability reasons (see next slide).
DP
z
1NDP
2NDP
42
Design Example (Continue)
Stability versus RESR
Phase margin versus RESRUGB versus RESR
Note: RESR was swept from 0 to 10
43
Design Example (Continue)System Simulation Results
Magnitude Plot (IL=50mA) Phase Plot (IL=50mA)
Magnitude Plot (IL=100µA) Phase Plot (IL=100µA)
DC Gain = 74dB
UGB = 6.3MHz
DC Gain = 75dB
UGB = 172KHz
Phase Margin = 90°
Phase Margin = 55°
44
Design Example (Continue)System Simulation Results
VIN Step Plot
Notes:1- VIN step from 3.4 to 3.5V
2- ILOAD step from 0 to 50mA
IL Step Plot
VV 30238.33
VV 30352.34
AVmA
mV
II
VV
LL
/0234.050
17.1
12
12 Load Regulation =
Line Regulation = VVmV
V
II
VV
LL
/0031.0100
313
12
12
VV 30206.32
VV 30238.31
45
Design Example (Continue)
System Simulation Results
PSR versus Frequency
PSR @ 100KHz = -35dB
46
Summary of the ResultsParameters Results
VIN 3.5V
VOUT 3.3V
ILoad_max
ILoad_min
50mA
0mA
IQ 30µA
PSRR@100KHz -35dB
Line Regulation 0.0031V/V
Load Regulation 0.0234V/A
TR 1µs
Technology 0.5µm CMOS
47
Current Efficient LDO
o
L
opassop C
I
CR
_
1
1
For low IL, for R1+R2 >> Ro_pass Note that RL is significantly larger
2oxp
p
C
L
WK
oamaEA
LEAv
L
LEAv
passompEAv
RgA
I
KAA
I
KIAA
RgAA
2
2
_passopasso RRRR _21_ )//(
For no-load current
par
bias
par
mQp C
KI
C
g 213
Loop Gain:
48
Current Efficient LDO
;/2
,3par
Lbiasloadp C
NIKI
oLoamaoLEAompEA
opassopassompEApv
CKIRgCKIACgAGB
CRRgAAGB
/2/2/
/ __1
LINote that GB will change as changes, this effects modify the pole-zero locations and the phase margin. i.e.,
1
1
poLEAMIN
poLEAMAX
; CKIAGB
; CKIAGB
/2
/2
min,
max,
Due to current mirror when load current exist, then we have
makeLL
p
L
loadp
I
GB
II
,1,3
11 22
2
2
2
Lparbias
o
par
oLbiaspar
NICIKNC
C or
CNIIKNC
The zero is located at:ESRo
CCz RCob
1|
Another pole is located at the output of the AEA,
paoap CR
12
G. A. Rincon-Mora, P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol.33, no.1, pp.36-44, Jan. 1998.
49
To determine the stability one can consider the open loop gain defined as:
321
111
1
ppp
z
vo
ref
fb
open
sss
sA
v
vA
where
passompoamavo RgRgA _321 ppzp
1
21
1
RR
p1 zp2 p3
Aopen
Avo
Stability imposes the following conditions: 1)( oopen
jA
Where o is defined as: Or 1)( oopen
jA 0)(oopen
jAARG where GBo
jAARGopenM
180Phase Margin:
3
1
2
1
1
11 tantantantan180pppz
M
50
For GBo ; M
is the arbitrary phase margin
3
1
2
111 tantantantan180pp
vo
z
o
M
GBGBA
In order to determine an approximated relation between p3 and GB several assumptions are required.
Avo >> 1, Then tan-1(Avo) 90°
vopasso
ESR
z
pvo
z
o AR
RA
_
1
opasso
paoavo
z
o
CR
CRA
_
Thus one can write
3
1
_
1
_
1 tantantan90p
voopasso
paoavo
passo
ESRMX
GBA
CR
CRA
R
R
51
Cadence Simulation
• This current efficient LDO is implemented using 0.5 μm CMOS process
• The LDO provides a 3.3 V regulated output voltage from a 3.5 V supply, for a load current IL ranging from 250 μA to 25mA
• The current in the buffer ranges from 20μA (which is only the bias current) in case of ILmin to 180µA in case of ILmax.
• The output voltage for load current alternating between ILmin and ILmax is shown.
52
Cadence Simulation
Fu ~ 0.78MHz
PM ~ 82°
Loop Gain ~ 52dB
MCR paoa
p 1.11
2
FCo
10 mRESR 100
mAiload 25
pFC par 3
kRoa 900 pFC pa 1
5.8_ passoR
VVout 3.3
400parR MCR parpar
p 33.8331
3
MCR oESR
z 11
KCR opasso
p 8.111
_1 FC
o10
53
Cadence Simulation
o
pM
GB89
33.833
78.02tan90tan90 1
3
1
• ωz cancels ωp2 and the phase margin can be approximated to:
• Which is close to the simulated value of 82o
• For the case of ILmin of 250µA, the dominant pole becomes even smaller and very far away from ωp3 and so the phase margin is almost 90o
• The step response for this case of ILmax is shown where Vin varies from 0 to 3.5V and accordingly Vo varies from 0 to 3.3V
54
Fu ~ 5.4MHz
PM ~ 90°
Loop Gain ~ 51.8dB
Simulation Results From Simulink
Loop Gain and Phase
55
Notes:1-Open Loop System2- The location of p3 was varied 3- The variation (p3) was simulated in Matlab using a “for loop”
Open Loop Gain and Phase For Different p3 Locations
PM 45°
p3 GBW
PM 90°p3 100GBW
56
Courtesy of Tuli Dake from TI
Current Limiters Architecture
57
ILIM Op Amp
58
References[1] G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS miller-compensated LDO regulator
with -27dB worst-case power-supply rejection using 60pF of on-chip capacitance ,” ISSCC, Feb. 2007.
[2] L.-G. Shen et al., “Design of low-voltage low-dropout regulator with wide-band high-PSR characteristic,” International Conference on Solid-State and Integrated Circuit Technology, ICSICT, Oct. 2006.
[3] R. J. Milliken, J. Silva-Martínez, and E. Sánchez-Sinencio, “Full on-chip CMOS low-dropout voltage regulator,” IEEE Trans. on Circuits and Systems – I, pp 1879-1890, vol. 54, Issue 9, Sept. 2007.
[4] C. K. Chava, and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 1041-1050, June 2004.
[5] K. N. Leung, and P.K.T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol.38, no.10, pp.1691-1702, Oct. 2003.
[6] K. C. Kwok, P. K. T. Mok. “Pole-zero tracking frequency compensation for low dropout regulator,” 2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735-738, May 2002.
[7] J. C. Teel, “Understanding noise in linear regulators” Analog Application Journal, 2Q 2005, www.ti.com/aaj
[8] K. N. Leung, P. K. T. Mok, and W. H. Ki, "A novel frequency compensation technique for low-voltage low-dropout regulator," IEEE International Symposium on Circuits and Systems, vol. 5, May 1999.
[9] G. A. Rincon-Mora and P. A. Allen, "A low-voltage, low quiescent current, low drop-out regulator," IEEE J. Solid-State Circuits, vol.33, no.1, pp.36-44, Jan. 1998.