How to Read PT Report
RTL Compiler Synthesis
1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.
Physical Synthesis Buffer Insertion, Gate Sizing, Wire Sizing,
Fast Buffer Insertion Considering Process Variation Jinjun Xiong, Lei He EE Department University of California, Los Angeles Sponsors: NSF, UC MICRO, Actel,
High-Performance Gate Sizing with a Signoff Timer
