1 Low Power Bus Encoding Technique Considering Coupling Effects Hsin-Wei Lin H.W. Lin is with the Graduate Institute of Integrated Circuit Design, National.
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A Survey and Comparison of Existing Low Power Ripple-Carry Adders
Cost Efficient Design of Reversible Adder Circuits for Low Power Applications
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11/11/2004Fei Hu, ELEC6970 Fall 20041 Power estimation techniques and a new glitch filtering effect modeling based on probability waveform Fei Hu Department.
Power Management Κωστή Ελένη Μ 487 Ραπτοπούλου Κλειώ Μ 515 Ψαρρά Τζένη Μ 510 Προηγμένη Αρχιτεκτονική Υπολογιστών.
A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique
Fei Hu Department of Electrical and Computer Engineering, Auburn University, AL 36849
Power Gating Structure for Reversible Programmable Logic Array
Finite State Machine State Assignment for Area and Power Minimization
Sram 2nd Phase
