Rectifier - Phase II
ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis: High-Level
A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation Final Project in RFCS in the MINT Program of the UPC by Sven Günther.
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation Keng-Jan Hsiao and Tai-Cheng Lee National Taiwan University Taipei, Taiwan.
THz/sub-THz direct detector challenges: rectification and thermal detectors for active imaging F. Sizov, V. Reva, O. Golenkov, V. Petriakov, A. Shevchik-Shekera,
ABSTRACT Introduction NEW Recursive DFT/IDFT architecture Low computation cycle 1/2: Chebyshev polynomial 2/N: Folded architecture High speed Register-splitting.
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation
Clock Generation for a SHA-less 10-bit 100Mhz Pipeline ADC Victor Lu, Pingli Huang, Yun Chiu
High-Voltage High Slew-Rate MOSFET Op-Amp Design 2005 Engineering Design Expo University of Idaho Erik J. Mentze Jennifer E. Phillips April 29, 2005 Project.
A True-Zero Load Stable Capacitor-Free CMOS Low Drop-out Regulator with Excessive Gain Reduction A True-Zero Load Stable Capacitor-Free CMOS Low Drop-out.
Digital Circuits to Compensate for Energy Harvester Supply Variation Hao-Yen Tang David Burnett.
1 Stephen Antosz Vice-Chair, IEEE Transformers Committee October 20, 2014 Washington, D.C. Transformers Committee Newcomers Orientation.
