Recording Synthesis History for Sequential Verification Robert Brayton Alan Mishchenko UC Berkeley.
Partial Scan Design with Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems, Circuits and Systems Research Lab Murray Hill, NJ 07974, USA.
Oct. 5, 2001Agrawal, Kim and Saluja1 Partial Scan Design With Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems Processor Architectures and.
Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns
Hardware and Petri nets
