Spring 2006EE 5324 - VLSI Design II - © Kia Bazargan 199 EE 5324 – VLSI Design II Kia Bazargan University of Minnesota Part V: Memory Design.
Objectives: Given input logice levels, state the output of an RS NAND and RS NOR. Given a clock signal, determine the PGT and NGT. Define “Edge Triggered”
