CCS Technical
Low power design-ver_26_mar08
AMD PowerTune & ZeroCore Power Technologies
Low-Power Design and Verification
Wireless Low Power and Verification Challenges
Kernel Features for Reducing Power Consumption on Embedded Devices
Tegra k1 trm_dp06905001_v02p
Prj2
Runtime Reconfigurable Network-on-chips for FPGA-based Systems
System on Chip Design and Modelling Dr. David J Greaves
Green Computing
Robust Low Power VLSI R obust L ow P ower VLSI A Programmable Multi- Channel Sub-Threshold FIR Filter for a Body Sensor Node Alicia Klinefelter Dept. of.
