bput_mtech_vlsi_2010
Nathan Eagle's presentation at eComm 2008
Vhdl Synthesis
High Speed Sequential IO on Windows NT™ 4.0 (sp3) Erik Riedel (of CMU) Catharine van Ingen Jim Gray
Model Checking Lecture 5. Outline 1 Specifications: logic vs. automata, linear vs. branching, safety vs. liveness 2 Graph algorithms for model checking.
