Physical Design Interview Questions
Advanced.asic.Chip.synthesis.using.synopsys.design.compiler.physical.com
Lect4 Design Tour
ECE 368 A Tour by Example of Non-Trivial Circuit Design and VHDL Description Lecture Notes # 4 Shantanu Dutt Electrical & Computer Eng. University of Illinois.
Automatic Gain Control Response Delay and Acquisition in Direct- Sequence Packet Radio Communications Sure 2007 Stephanie Gramc Dr. Noneaker.
