Dst
Asynchronous Circuits Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona Collège de France May 14 th, 2013.
Timing¬Driven Variation¬Aware NonuniformClock Mesh Synthesis
physical design essentials
Force-Directed List Scheduling for DMFBs Kenneth ONeal, Dan Grissom, Philip Brisk Department of Computer Science and Engineering Bourns College of Engineering.
High-Level Synthesis for FPGAs: From Prototyping to Deployment (To appear in IEEE TCAD 2011) Course Presentation By: Murtaza Merchant 1.
Fault Diagnosis
Synthesis of Speed Independent Circuits Based on Decomposition
Power Minimization for LED-backlit TFT-LCDs
Incremental Transient Simulation of Power Grid
Constraint-Driven Large Scale Circuit Placement Algorithms
A Spectral Clustering Approach to Optimally Combining Numerical Vectors with a Modular Network
