A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks Tan Yan*, Shuting Li Yasuhiro Takashima, Hiroshi Murata The University.
MIP-based Detailed Placer for Mixed-size Circuits Shuai Li, Cheng-Kok Koh ECE, Purdue University {li263, chengkok}@purdue.edu.
Placer Suboptimality Evaluation Using Zero-Change Transformations Andrew B. Kahng Sherief Reda VLSI CAD lab UCSD ECE and CSE Departments.
