Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
High-Speed and Low-Power On-Chip Global Link Using Continuous-Time Linear Equalizer
High-Speed and Low-Power On-Chip Global Link Using Continuous-Time Linear Equalizer Yulei Zhang 1, James F. Buckwalter 1, and Chung-Kuan Cheng 2 1 Dept.
EEWeb Pulse - Issue 72
Wire Bulletin - Jan 11
