Seminar Report
22 nano meter technology
3D or Tri-gate transistors
Low-power FinFET Circuit Design Niraj K. Jha Dept. of Electrical Engineering Princeton University Joint work with: Anish Muttreja and Prateek Mishra.
Top-Gate Transistors Using Bismuth-Selenide & Indium-Arsenide Nanowires The purpose of this project was to investigate whether the use of top-gated transistors.
Sushant
Stephen Thophd Thesis
Safety Engineers. The Naval Ordnance Safety and Security Activity (NOSSA) realized the need to educate and inform the Safety Professionals on CPLDs.
FinFETs: From Circuit to Architecture Niraj K. Jha Dept. of Electrical Engineering Princeton University Joint work with: Anish Muttreja, Prateek Mishra,
05.10.20151/38 Lifetime Management of Flash-Based SSDs Using Recovery-Aware Dynamic Throttling Sungjin Lee, Taejin Kim, Kyungho Kim, and Jihong Kim Seoul.
