3d ICs Full Seminar Report 2
3d i cs_full_seminar_report
Intelligent RAM
EE141 1 Memory STMicro/Intel/UCSD/THNU DRAM: Dynamic RAM Store their contents as charge on a capacitor rather than in a feedback loop. 1T dynamic RAM.
Caches Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University See P&H 5.1, 5.2 (except writes)
Interconnection and Packaging in IBM Blue Gene/L
Performance Evaluation of Two Emerging Media Processors: VIRAM and Imagine
Caches
Embedded DRAM for a Reconfigurable Array S.Perissakis, Y.Joo 1, J.Ahn 1, A.DeHon, J.Wawrzynek University of California, Berkeley 1 LG Semicon Co., Ltd.
Interconnection and Packaging in IBM Blue Gene/L Yi Zhu Feb 12, 2007.
