Diagnostic Test Generation for Path Delay Faults in a Scan Circuit
06/08/2015 Diagnostic Test Generation for Transition Delay Faults Using Two-Timeframe ATPG Model Master’s Thesis Defense Xiaolu Shi Dept. of ECE, Auburn.
1 Design Validation and Debugging Tim Cheng Department of Electrical & Computer Engineering UC Santa Barbara VLSI Design and Education Center (VDEC) Univ.
