Gate Sizing for Cell Library Based Designs Shiyan Hu*, Mahesh Ketkar**, Jiang Hu* *Dept of ECE, Texas A&M University **Intel Corporation.
A Faster Approximation Scheme for Timing Driven Minimum Cost Layer Assignment
Battery Aware Dynamic Scheduling for Periodic Task Graphs
Clock recovery by FP-FBGs –How things shape up? e source line width is narrower than the resonator bandwidth. Optical Clock Recovery with Fabry-Perot Filter.
Fast Algorithms for Slew Constrained Minimum Cost Buffering
Second Generation (2G) Cellular
12
SAMPADA-11
Module_3(3)
School of Engineering and Technology Nagaland University
