Page 1 Department of Electrical Engineering National Chung Cheng University, Chiayi, Taiwan Power Optimization for Clock Network with Clock Gate Cloning.
1 L22 : Clock Issues in Deep Submircron Design 1999. 10 Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Mail : [email protected]@skku.ac.kr Homepage : vada.skku.ac.kr.
