Sioux Hot-or-Not: Functional programming: unlocking the real power of multi-core (Joe Armstrong)
1 Next Generation On-Chip Networks: What Kind of Congestion Control Do We Need? George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu Carnegie Mellon.
Slide_1 A Survey of Architectural Design and Implementation Tradeoffs in Network on Chip Systems Dan Marconett Next-Generation Networking Systems Lab University.
A Case for Wireless 3D NoCs for CMPs Hiroki Matsutani (1), Paul Bogdan (2), Radu Marculescu (2), Yasuhiro Take (1), Daisuke Sasaki (1), Hao Zhang (1),
COEN-4790 Developments in Computer Hardware Lecture #1 Networks-on-Chip (NoC) 1 Cristinel (Cris) Ababei Dept. of Electrical and Computer Engr., Marquette.
Department f Computer Engineering Malaviya National Institute of Technology, Jaipur India (PROM3D) Parameterized Path-Based, Randomized, Oblivious, Minimal.
Energy and latency aware application
Conference on Adaptive Hardware and Systems (AHS'14) - The DSP for FlexTiles
Runtime Reconfigurable Network-on-chips for FPGA-based Systems
Coarse grained hybrid reconfigurable architecture
Coarse grained hybrid reconfigurable architecture with no c router
Coarse grained hybrid reconfigurable architecture with noc router for variable block size motion estimation