Delay models (I) A B C Real (analog) behaviorAbstract behavior A B C Abstractions are necessary to define delay models manageable for design, synthesis.
Play Framework Cookbook - Second Edition - Sample Chapter
09. User Input
Jordi Cortadella, Universitat Politecnica de Catalunya, Barcelona Mike Kishinevsky, Intel Corp., Strategic CAD Labs, Hillsboro.
1 Logic synthesis from concurrent specifications Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain In collaboration with M. Kishinevsky,
Bridging the gap between asynchronous design and designers Part II: Logic synthesis from concurrent specifications.
Synthesis of asynchronous circuits from petri nets
Elasticity and petri nets
