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SpW-10X Router ASIC Testing and Performance Steve Parkes, Chris McClements, Space Technology Centre, University of Dundee Gerald Kempf, Christian Gleiss,

Fig.2: Carry chain delay line: (a) logic block diagram; (b) layout obtained; (c) simplified block diagram of the Virtex 5 slice. Principle of operations.

SpW-10X Router ASIC Testing and Performance

Fig.2: Carry chain delay line: (a) logic block diagram; (b) layout obtained ;