Evaluation of High Speed and Low Memory Parallel Prefix Adders
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
brent kung adder
Dual-Threshold Voltage Design of Sub-threshold Circuits Jia Yao Dept. of ECE, Auburn University Doctoral Final Examination Dissertation Committee: Dr.
A Tutorial on Battery Simulation - Matching Power Source to Electronic System Manish Kulkarni and Vishwani D. Agrawal Auburn University Auburn, AL 36849,
Caches prepared and Instructed by Shmuel Wimer Eng. Faculty, Bar-Ilan University Cashes1.
Word-Size Optimization for Low Energy, Variable Workload Sub-threshold Systems Sudhanshu Khanna, Anurag Nigam ECE 632 – Fall 2008 University of Virginia.
Caches
