Gazing Into The Void
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Transcript of Gazing Into The Void
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Prof. Ian PhillipsPrincipal Staff Eng’r,
Visiting Prof. at ...
Many-Core Workshop
Contribution to Industry Award 2008
y pNEC, Birmingham
19mar12Award 2008
The closer you are to death; the more you realize you are alive.
The closer you are to death; the harder you cling to life.
Top 5000 J.Simpson, Touching the Void, 1985
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Moore’s Law: c1965 “Moore's Law” was coined by Carver Mead in 1970, from Gordon
Moore's article in Electronics Magazine 19 April 1965 "Cramming more components onto integrated circuits“components onto integrated circuits .
“The complexity for minimum p ycomponent costs has increased at a rate of roughly a factor of two per year ...Certainly over the short term this rate can be
t d t ti if t t i Oexpected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at y fleast 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such
l i it b b ilt i l f ”a large circuit can be built on a single wafer”
In 1965 he was designing ICs with ~50 transistors!
Gordon Moore, Founder of Intel
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g gMoore’s Law has held for ~50 years ... Taking us to 100B transistor ICs
Moore’s Law ...10nm
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100nm
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ITRS’99
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All Exponentials Have Got to End ...
130nm
90nm
30nm
1414nm
7nm7nm
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All Exponentials Have Got to End ... Growing opinion that 14 or 7nm will be the
smallest yieldable node (any process).130nm
90nm Just 3-4 gen. (5-8yr) to the
end of Planar Scaling
O l thi30nm
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Only things on the drawing board today ...
14nm
7nm... can get into the last of the of planar chips! 7nmlast of the of planar chips!
Its the end-of-the-road for ‘promising technologies’ ! Clean-Sheet Synthesis Scalable Processor Arrays Formal Design ...The future lies with Hybrid,
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Formal Design Top-Down Design Evolutionary Architectures
Moore’s Law ...10nm
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ITRS’99
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What Happened to the Productivity Gaps?
Reuse Happened ! <1995 chip design was entire ... Moore’s Law was handled by Bigger Teams and Faster Tools With Improved Productivity through HDL and Synthesis
>1995 reuse quietly entered the picture ... Circuit Blocks
... With Supporting
Methodology!
Circuit Blocks CPUs (and Software) External IP
Methodology!
(Incl. Software) Up-Integration Chip Reuse (ASSP)
Delivering Productivity Quality and Reliability... Delivering Productivity, Quality and Reliability ... Birth of HW/SW IP Companies (eg ARM)
... But brought Architectural Chaos & Commoditisation of FABs
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... But brought Architectural Chaos & Commoditisation of FABs
Products Make Money 21c Businesses have to be Selling things that People (End-Customers) want to buy. Operations and Competition is Global and so are InvestorsOperations and Competition is Global and so are Investors Nationality has little meaning
Business needs End-Customers buy Functionality not Technology
Technologies enable Product Options Business-Models make Money
New Products are Design is a Cost/Risk to be Minimised
T h l (HW SW M h i O ti t ) Technology (HW, SW, Mechanics, Optics, etc) is (just) a means to a Product end!
New Technology increases Cost/Risk ... But not always Value
... Globalisation makes Business Focus on their Core-Competence!
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Architecting an iConic Many-Core Product ...
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It’s Not Solid Obsidian !?!Down 1-Level:
Modules
The Control Board.
10 Source ... http://www.ifixit.com
The Control Board (A-side)
Down 2-Levels: Sub-Assemblies Visible Design-Team Members ...
Samsung (flash memory) - (ARM Partner) Cirrus Logic (audio codec) - (ARM Partner)g ( ) ( ) AKM (Magnetic Sensor) Texas Instruments (Touch Screen Controller and mobile DDR) - (ARM Partner)
Invisible Design-Team Members ...g Software Tools, OS & Drivers, GSM Security; Graphics, Video and Sound ... Manufacturing, Assembly, Test, Certification ...
11 Source ... http://www.ifixit.com
The Control Board (B-side)
Down 2-Levels: Sub-Assemblies Visible Design-Team Members...
A4 P ifi d b A l d i d d f t d b S A4 Processor, specified by Apple, designed and manufactured by Samsung ... The central unit that provides the iPhone 4 with its GP computing power. Reported to contain ARM A8 600 MHz CPU (other ARM CPUs and IP)
ST-Micro (3 axis gyroscope) - (ARM Partner) Broadcom (Wi-Fi, Bluetooth, and GPS) - (ARM Partner) Skyworks (GSM)
Many Processors & Software ..with..
Hybrid and Evolutional Architecture !
GPS
Triquint (GSM PA) Infineon (GSM Transceiver) - (ARM Partner)
Hybrid and Evolutional Architecture !
GPS
Bluetooth, EDR &FM
12 Source ... http://www.ifixit.com
Multicore ARM On-Chip ... Heterogeneous Multicore Systems have existed for a long time:
Power ManagerApplication UI & 3D graphics
Cortex™-A8Mali™-400
MP Cortex-M3
Interconnect
Memory
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Coherent Multicore Cluster Homogenous Multicore cluster, as part of a heterogeneous system:
… Power ManagerUser Interface
and 3D graphicsCortex-A9 Cortex-A9
…
Coherency Logic
gg p
Coherency LogicMali-400 MP Cortex-M3
Interconnect
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Multiple Clusters Multiple Homogeneous Coherent Clusters
Cortex-A15…
Cortex-A15 Cortex-A15…
Cortex-A15
Coherency Logic in L2 Cache Coherency Logic in L2 Cache
Coherent Interconnect
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Multi-Processors on a ChipUsers require a pocket ‘Super-Computer’ ... Silicon Technology Provides a few-Billion raw transistors ... ARM’s IP makes it Practical to utilise them ...
• 10 Programmable Processors• 10 Programmable Processors• 4 x A9 Processors (2x2):• 4 x MALI 400 Fragment Proc:• 1 x MALI 400 Vertex Proc
11 Processors But the Chip Architecture isalso Hybrid and Evolutional !• 1 x MALI 400 Vertex Proc.
• 1 x MALI Video CoDec• Software Stacks, OS’s and
Design Tools/
also Hybrid and Evolutional !
Design Tools/• ARM Technology gives
chip/system designers a good start Andgood start. And ...
• Improves Productivity• Improves TTM
I Q lit /C t i t
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• Improves Quality/Certainty
nVidea Tegra 3 Processor (~1B transistors)
nVidea Tegra3
ARM
ARMARM
ARM
ARMARM
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The Apple A4 SIP Package (Cross-section)
Memory ‘Package’
P SOC Di
2 Memory Dies‘Package’
Processor SOC DieGlue4-Layer Platform
Package’
IC Packaging
Package
IC Packaging The processor is the centre rectangle. The silver circles beneath it are solder balls. Two rectangles above are RAM die, offset to make room for the wirebonds.
Putting the RAM close to the processor reduces latency, making RAM faster and cuts power.g p y, g p Unknown Mfr (Memory) Samsung/ARM (Processor) Unknown (SIP Technology)
18 Source ... http://www.ifixit.com
3D: Keeping Moore’s Law Going
Many More ‘Cores’ Many-More Cores ...Hardware and Software ...
Very-Hybrid Architecture ...E M P P bl Even-More Power Problems ...
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Reliability and Robustness As Process Geometry falls; Reliability and Robustness does as well Susceptibility to high-energy particles Wear-out mechanisms Variability State-dependencyState depe de cy Imperfection in design
Current 3D techniques are even more vulnerable to defects Throw away good chiplets with the bad-ones Additional chiplet/chiplet interactions Can’t fully test chiplets before assemblyCan t fully test chiplets before assembly Increased assembly loss/imperfections Limited re-working potential
Must break the 100% functionality requirement Requires Functional on Imperfect (Design) Platforms
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The Failure of Power ScalingNode 45nm 22nm 11nm
Year 2008 2014 2020
Area-1
Peak freq
1
1
4
1 6
16
2 4Peak freq
Power
1
1
(4 x 1)-1 = 25% (16 x 0.6)-1 = 10%
1.6
1
2.4
0.6
Exploitable Si
Dark Silicon
Dark Silicon
(in 45nm power budget)
25% 10%
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Source: ITRS 2008 … Severely limits the circuitry we can Turn On !
Conclusions Planar Processing ends in 3-5yrs And takes with it all clean-sheet planar design possibilities 3D takes Moore's Law into its next decade
Productivity through Reuse is Business Imperative ‘Productivity Aids’ without Methods and Legacy Compatibility are UselessProductivity Aids without Methods and Legacy Compatibility are Useless.
Multi-Processor Architecture is driven by the System Functionality They will always be: Multi-Discipline, Multi-Process, Multi-Geometry,
Multi-Architecture, Multi-Company, Multi-Die and Multi-Chip. All Architectures will be Hybrid and Evolutionary
Power Efficiency is not just a Societal IssuePower Efficiency is not just a Societal Issue We cannot use what we can create without overcoming it (We need x100!)
Business only needs to be “better” than its competitors Good enough; is enough.
Cannot depend on 100% functionality any more Need F nctionalit despite imperfection in Design and Man fact re
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Need Functionality despite imperfection in Design and Manufacture
Multi-Processing: Just a means to an end!
Its the System Stupid 23
Its the System Stupid