Virtex-6 FPGAGTX Transceiver Characterization ReportPCI Express 2.0 (2.5 and 5.0 Gb/s) Electrical Standard
RPT121 (v1.0) November 3, 2010
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Revision HistoryThe following table shows the revision history for this document.
Date Version Revision
11/03/10 1.0 Initial Xilinx release.
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Virtex-6 FPGA GTX Transceiver Characterization Report for the PCI Express 2.0 Electrical Standard
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Transceiver Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Electrical Characterization Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Add-in Card Transmitter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Test Results for the 2.5 Gb/s Line Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13SIGTEST Results for the 2.5 Gb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Test Results for the 5.0 Gb/s Line Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18SIGTEST Results for the 5.0 Gb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Transmitter Differential and Common Mode Return Loss. . . . . . . . . . . . . . . . . . . . 24Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Test Results for Transmitter Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PLL Bandwidth Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Test Results for the 2.5 Gb/s Line Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Test Results for the 5.0 Gb/s Line Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Receiver Input Jitter Tolerance Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Test Results for the 5.0 Gb/s Line Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Receiver Differential and Common Mode Return Loss . . . . . . . . . . . . . . . . . . . . . . . 37Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Test Results for Receiver Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table of Contents
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Virtex-6 FPGA GTX Transceiver Characterization Report for the PCI Express 2.0 Electrical Standard
IntroductionThis characterization report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the PCI Express® Revision 2.0 specifications published in the PCI Express Base Specification, Revision 2.1 and the PCI Express Card Electromechanical Specification, Revision 2.0. All testing for this report is based on line rates of 2.5 and 5.0 Gb/s across voltage, temperature, and worst-case transceiver performance corners.
This report includes test results for these PCI Express, Revision 2.0 specifications:
• Add-in Card Transmitter Test, page 9
• 2.5 Gb/s Line Rate
- Unit Interval
- Template Tests
- Peak Differential Output Voltage
- Eye Width
- Median to Maximum Jitter
• 5.0 Gb/s Line Rate
- Unit Interval
- Template Test
- Peak Differential Output Voltage
- Eye Width
- Deterministic Jitter
- Total Jitter at BER–12
• Transmitter Differential and Common Mode Return Loss, page 24
• PLL Bandwidth Test, page 26
• Receiver Input Jitter Tolerance Test, page 32
• Receiver Differential and Common Mode Return Loss, page 37
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Test Conditions
Test ConditionsTable 1 and Table 2 show the supply voltage and temperature conditions used in the characterizations, respectively. All combinations of voltage and temperature conditions are used for the tests performed.
Transceiver SelectionXilinx first performs volume generic transceiver characterization across process, voltage, and temperature. The generic data can be found in RPT120, Virtex-6 FPGA GTX Transceiver Characterization Report. Protocol-specific characterization is subsequently performed using representative transceivers from generic characterization.
The chosen Virtex-6 FPGA GTX transceiver channels represent a mixture of transmitters and receivers having worst-case and typical performance based on volume generic characterization data. Transceivers with the worst performing transmitter output jitter and receiver jitter tolerances are selected within the worst-case distribution of the transceivers found in the generic volume characterization. The histograms in this characterization report do not show a true statistical representation normally present in a random (or even typical) population. The histograms are skewed toward the worst-case performance because of the transceiver selection process and are not representative of the typical production silicon.
Table 1: Supply Voltage Test Conditions
Condition MGTAVCC (V) MGTAVTT (V)
VMIN Note(1) 1.14
VMAX Note(1) 1.26
Notes: 1. Refer to DS152, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics, for the MGTAVCC values.2. Other FPGA voltages stay at their nominal values during the test.
Table 2: Temperature Test Conditions
Condition Temperature (°C)
T–40 –40
T0 0
T100 100
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Summary of Results
Summary of ResultsTable 3 and Table 4 show the tested Virtex-6 FPGA GTX transceiver performance results against the PCI Express Base Specification, Revision 2.1 and the PCI Express Card Electromechanical Specification, Revision 2.0. The data reported in these tables represents the values obtained under the worst-case voltage, temperature, and performance corner conditions.
Table 3: PCI Express 2.0 Characterization Summary of Results for 2.5 Gb/s Line Rate
Test Name Parameter SpecificationWorst-CaseTest Result
Units Compliant
Unit Interval(1) Minimum 399.88 400.03 ps Yes
Maximum 400.12 400.04 ps Yes
Template Tests(1)Maximum
Zero Mask Failure
ZeroNumber of
failuresYes
Peak Differential Output Voltage(1) Minimum 360 Programmable mV Yes
Maximum 1200 Programmable mV Yes
Minimum Eye Width(1) Minimum 287 334.6 ps Yes
Median to Max Jitter(1) Maximum 56.5 30.08 ps Yes
TX Differential Return Loss Frequency Profile
See Figure 20 dB Yes
TX Common Mode Return Loss Frequency Profile
See Figure 21 dB Yes
PLL Bandwidth Minimum 1.5 4.00 MHz Yes
Maximum 22 15.00 MHz Yes
PLL Peaking Maximum 3 1.32 dB Yes
RX Differential Return Loss Frequency Profile
See Figure 34 dB Yes
RX Common Mode Return Loss Frequency Profile
See Figure 35 dB Yes
Notes: 1. Part of the Add-in Card Transmitter test for PCI Express, Revision 2.0.
Table 4: PCI Express 2.0 Characterization Summary of Results for 5.0 Gb/s Line Rate
Test Name Parameter SpecificationWorst-CaseTest Result
Units Compliant
Unit Interval(1) Minimum 199.94 200.01 ps Yes
Maximum 200.06 200.01 ps Yes
Template Tests(1)Maximum
Zero Mask Failure
Zero Number of failures
Yes
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Summary of Results
Peak Differential Output Voltage(1) Minimum 380 Programmable mV Yes
Maximum 1200 Programmable mV Yes
Minimum Eye Width(1),(2) Minimum 126 131.94 ps Yes
Deterministic Jitter(1),(2) Maximum 54 15.88 ps Yes
Total Jitter at BER–12(1),(2) Maximum 74 68.06 ps Yes
TX Differential Return Loss Frequency Profile
See Figure 20 dB Yes
TX Common Mode Return Loss Frequency Profile
See Figure 21 dB Yes
PLL Bandwidth Minimum 5 5.48 MHz Yes
Maximum 16 14.00 MHz Yes
PLL Peaking Maximum 1 0.96 dB Yes
RX Input Jitter Tolerance TJ (not including SJ)
See Table 18(3) UI Yes
SJ at 22.82 MHz(4)
Not defined 0.22 UI Yes
RX Differential Return Loss Frequency Profile
See Figure 34 dB Yes
RX Common Mode Return Loss Frequency Profile
See Figure 35 dB Yes
Notes: 1. Part of the Add-in Card Transmitter test for PCI Express, Revision 2.0.2. Without crosstalk.3. Total jitter components and amplitude specification limits are defined in the table called “5.0 GT/s Tolerancing Limits for Common
Refclk Rx Architecture” from the PCI Express Base Specification, Revision 2.1.4. BER = 10–12.
Table 4: PCI Express 2.0 Characterization Summary of Results for 5.0 Gb/s Line Rate (Cont’d)
Test Name Parameter SpecificationWorst-CaseTest Result
Units Compliant
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Electrical Characterization Details
Electrical Characterization DetailsThis section describes the test methodology used to characterize the Virtex-6 FPGA GTX transceiver's performance against the PCI Express Base Specification, Revision 2.1 and the PCI Express Card Electromechanical Specification, Revision 2.0. The Virtex-6 FPGA GTX transceiver under test is configured using the default PCI Express setting generated from the Virtex-6 FPGA GTX Transceiver Wizard, version 1.6. The Virtex-6 FPGA GTX transceiver attribute settings that differ from the Wizard default settings are identified in the “Test Setup and Conditions” table for each test. Table 5 shows the PLL settings used in the characterization. This characterization report is based on the 100 MHz reference clock. The 125 MHz and 250 MHz reference clock PLL settings are provided as a comparison.
Add-in Card Transmitter Test
Test MethodologyThe Add-in Card Transmitter test for the 2.5 Gb/s line rate comprises the unit interval, template tests, peak differential output voltage, eye width, and median to maximum jitter tests. For the 5.0 Gb/s line rate, the test comprises the unit interval, template tests, peak differential output voltage, eye width, deterministic jitter, and total jitter tests. These tests are compared against the PCI Express Card Electromechanical Specification, Revision 2.0. The Add-in Card Transmitter specification for the 2.5 and 5.0 Gb/s line rates is defined in Table 6 and Table 7, respectively. ps
Table 5: PLL Settings for 2.5 Gb/s and 5.0 Gb/s Line Rate
Data Rate (Gb/s)
PLL Frequency
(GHz)
Reference Clock Frequency
(MHz)
Reference Clock Divider: M(1)
PLL Feedback Dividers:
N1(2) x N2(3)
PLL Output Divider:
D(4)
2.5 2.5 100 1 5 x 5 = 25 2
2.5 2.5 125 1 5 x 4 = 20 2
2.5 2.5 250 1 5 x 2 = 10 2
5.0 2.5 100 1 5 x 5 = 25 1
5.0 2.5 125 1 5 x 4 = 20 1
5.0 2.5 250 1 5 x 2 = 10 1
Notes: 1. M = [TX/RX]PLL_DIVSEL_REF.2. N1 = [TX/RX]PLL_DIVSEL45_FB.3. N2 = [TX/RX]PLL_DIVSEL_FB.4. D = [TX/RX]PLL_DIVSEL_OUT.
Table 6: Add-in Card Transmitter Specification for the 2.5 Gb/s Line Rate
Test Name Specification Range Units
Unit Interval (UI) 399.88 to 400.12 ps
Template Tests Zero Eye Mask Failures Number of failures
Peak Different Output Voltage 360 to 1200 mV
Eye Width 287 (minimum) ps
Median to Maximum Jitter 56.5 (maximum) ps
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Add-in Card Transmitter Test
These tests are performed using the test setup shown in Figure 1. An Agilent Infiniium DSA91304A Digital Signal Analyzer installed with a PCI Express automated test application performs the Add-in Card Transmitter test using the test methodology defined in the PCI-SIG® document PCI Express 2.0 CEM Signal Quality Testing for Add-in Cards using Agilent DSO91304A, and DSA91304A 13 GHz Real-Time Oscilloscopes. Agilent DSA91304A Analyzer calibration is performed prior to data collection.
The Virtex-6 device under test is configured to PCI Express mode and set to transmit the PCI Express compliance pattern on all available TX lanes of the ML623 Virtex-6 FPGA GTX Transceiver Characterization Board. Table 8 defines the test setup and conditions for the Add-in Card Transmitter test.
Table 7: Add-in Card Transmitter Specification for the 5.0 Gb/s Line Rate
Test Name Specification Range Units
Unit Interval (UI) 199.94 to 200.06 ps
Template Tests Zero Eye Mask Failures Number of failures
Peak Different Output Voltage 380 to 1200 mV
Eye Width(1) 126 (minimum) ps
Deterministic Jitter(1) 54 (maximum) ps
Total Jitter at BER–12(1) 74 (maximum) ps
Notes: 1. Without crosstalk.
X-Ref Target - Figure 1
Figure 1: Add-in Card Transmitter Test Setup Block Diagram
SMA-SMP matched pair cables fromthe PCI Express CBB to the AgilentDSA91304A Scope.
SMA-SMA matched pair cables fromthe ML623 Characterization Board tothe SMA to PCIe Adapter for the TXlane under test.
SMA-SMA matched pair cables fromthe SMA to PCIe Adapter to the ML623Characterization Board for the 100 MHzreference clock.
DC Blocks
50Ω Termination
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CLKIN
ML623 Characterization Board
Virtex-6XC6VLX240TFF1156 FPGA
TI FusionPowerModule
SMA to PCIeAdapter
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Add-in Card Transmitter Test
Table 8: Add-in Card Transmitter Test Setup and Conditions
Parameter Value
Measurement Instrument
Agilent Infiniium DSA91304A Digital Signal Analyzer:
• AC coupled using DC blocks.
Software Application
• Agilent N5393B PCI Express Automated Test Application Version 2.10: • Installed on the Agilent DSA91304A scope to automate the Add-in
Card Transmitter test.• PCI-SIG accepted methodology.
• SIGTEST 3.1.9:• Used only to compare the measurement results with the Agilent PCI
Express automated test application.• Uses the setup described in Figure 1. • PCI-SIG accepted methodology.
Voltage TI Fusion Power Module:
• Installed on the ML623 board to change the MGTAVTT and MGTAVCC voltages between VMIN and VMAX.
Temperature Temperature Unit:
• A socket attached with a temperature controller is used to change the temperature condition of the device under test between T–40, T0, and T100.
Data Pattern Transmitting the PCI Express compliance pattern on all available TX lanes of the ML623 board.
FPGA Virtex-6 FPGA XC6VLX240T FF1156.
Load Boards • ML623 Virtex-6 FPGA GTX Transceiver Characterization Board, Revision C: • 50Ω terminator on TX channels not under test.• On the various ML623 board channels used, there are about 4 to 8
inches of FR4 in the TX paths.• PCI Express Compliance Base Board (CBB), Revision 2.0:
• Standard PCI-SIG board for the Add-in Card Transmitter Test.• SMA to PCIe® Adapter, Revision D:
• Used to connect the ML623 board to the x16 interface of the PCI Express CBB.
Cables • One pair of matched 50Ω Rosenberger SMA-SMP cables from the PCI Express CBB to the Agilent DSA91304A oscilloscope.
• One pair of matched 50 Ω SMA-SMA cables from the SMA to PCIe Adapter to the ML623 board for the 100 MHz reference clock.
• One pair of matched 50Ω SMA-SMA cables from the ML623 board to the SMA to PCIe Adapter for the TX lane under test.
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Add-in Card Transmitter Test
GTX Transceiver Attributes
• TX Amplitude and Pre-Emphasis:• TX_DRIVE_MODE = PIPE• TXDEEMPH = 1'b1• TXSWING = 1'b0• TXMARGIN = 3'b000• TX_DEEMPH_1 = 5'b10010• TX_MARGIN_FULL_0 = 7'b1001101
• PLL Charge Pump Configuration:• TXPLL_CP_CFG = 8'h05• RXPLL_CP_CFG = 8'h05
Reference Clock 100 MHz sourced from the PCI Express CBB.
Table 8: Add-in Card Transmitter Test Setup and Conditions (Cont’d)
Parameter Value
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Add-in Card Transmitter Test
Test Results for the 2.5 Gb/s Line RateFigure 2 is a transition eye diagram, and Figure 3 is a non-transition eye diagram generated from the Agilent PCI Express automated test application. The Add-in Card Transmitter unit interval test reported UI between 400.03 ps and 400.04 ps, and template tests reported zero eye mask failures. X-Ref Target - Figure 2
Figure 2: Transition Eye Diagram for the 2.5 Gb/s Line Rate
X-Ref Target - Figure 3
Figure 3: Non-Transition Eye Diagram for the 2.5 Gb/s Line Rate
RPT121_02_051210
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Add-in Card Transmitter Test
Figure 4 shows the peak differential output voltage results, Figure 5 shows the eye width results, and Figure 6 shows the median to maximum jitter results at a 2.5 Gb/s line rate with a 100 MHz reference clock. These histogram results are skewed towards the worst-case performance because of the transceiver selection process. The vertical axis of the histogram represents the frequency or number of data points. Additional output jitter margin can be gained by using a 125 MHz or 250 MHz reference clock. Table 9 summarizes the maximum and minimum Add-in Card Transmitter test results at the 2.5 Gb/s line rate with a 100 MHz reference clock. X-Ref Target - Figure 4
Figure 4: Peak Differential Output Voltage for the 2.5 Gb/s Line Rate
X-Ref Target - Figure 5
Figure 5: Eye Width for the 2.5 Gb/s Line Rate
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Add-in Card Transmitter Test
SIGTEST Results for the 2.5 Gb/s Line RateFigure 7 shows a transition eye diagram, and Figure 8 shows a non-transition eye diagram generated from the SIGTEST application. The SIGTEST results were used only to compare the measurement results from the Agilent PCI Express automated test application. Figure 9 shows the summary of a SIGTEST result.
X-Ref Target - Figure 6
Figure 6: Median to Maximum Jitter for the 2.5 Gb/s Line Rate
Table 9: Minimum and Maximum Test Results for the 2.5 Gb/s Line Rate
Test Name Minimum Maximum Units
Unit Interval (UI) 400.03 400.04 ps
Template TestsZero Zero
Number of failures
Peak Differential Output Voltage
505.0 646.4 mV
Eye Width 334.60 363.32 ps
Median to Maximum Jitter 18.26 30.08 ps
Notes: 1. In PCI Express mode, the TX_DRIVE_MODE is set to PIPE and the Peak Differential Output
Voltage is programmable by setting TXDEEMPH and TXMARGIN.2. Additional output jitter margin can be gained by using a 125 MHz or 250 MHz reference clock.
This is based on using an external ICS874002AG-02 EVB PCI Express Jitter Attenuator with an onboard ICS874003-05 PCI Express Jitter Attenuator that can be used to convert the 100 MHz reference clock from the PCI Express CBB to 125 MHz or 250 MHz. This PCI Express Jitter Attenuator meets the PLL bandwidth and peaking requirements.
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Add-in Card Transmitter Test
X-Ref Target - Figure 7
Figure 7: SIGTEST Transition Eye Diagram for the 2.5 Gb/s Line Rate
X-Ref Target - Figure 8
Figure 8: SIGTEST Non-Transition Eye Signal Diagram for the 2.5 Gb/s Line Rate
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Add-in Card Transmitter Test
X-Ref Target - Figure 9
Figure 9: SIGTEST Result for the 2.5 Gb/s Line Rate
RPT121_09_051210
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Add-in Card Transmitter Test
Test Results for the 5.0 Gb/s Line RateFigure 10 is a transition eye diagram, and Figure 11 is a non-transition eye diagram generated from the Agilent PCI Express automated test application. The Add-in Card Transmitter unit interval test reported UI of 200.01 ps, and template tests reported zero eye mask failures. X-Ref Target - Figure 10
Figure 10: Transition Eye Diagram for the 5.0 Gb/s Line Rate
X-Ref Target - Figure 11
Figure 11: Non-Transition Eye Diagram for the 5.0 Gb/s Line Rate
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Add-in Card Transmitter Test
Figure 12 shows the peak differential output voltage results, Figure 13 shows the eye width results, Figure 14 shows the deterministic jitter results, and Figure 15 shows the total jitter results at the 5.0 Gb/s line rate with a 100 MHz reference clock. These histogram results are skewed towards the worst-case performance because of the transceiver selection process. The vertical axis of the histogram represents the frequency or number of data points. Additional output jitter margin can be gained by using a 125 MHz or 250 MHz reference clock. Table 10 summarizes the maximum and minimum Add-in Card Transmitter test results at the 5.0 Gb/s line rate with a 100 MHz reference clock. X-Ref Target - Figure 12
Figure 12: Peak Differential Output Voltage for the 5.0 Gb/s Line Rate
X-Ref Target - Figure 13
Figure 13: Eye Width for the 5.0 Gb/s Line Rate
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Add-in Card Transmitter Test
X-Ref Target - Figure 14
Figure 14: Deterministic Jitter for the 5.0 Gb/s Line Rate
X-Ref Target - Figure 15
Figure 15: Total Jitter for the 5.0 Gb/s Line Rate
Table 10: Minimum and Maximum Test Results for the 5.0 Gb/s Line Rate
Test Name Minimum Maximum Units
Unit Interval (UI) 200.01 200.01 ps
Template TestsZero Zero
Number of failures
Peak Differential Output Voltage
671.5 845.9 mV
Eye Width(1) 131.94 157.01 ps
Deterministic Jitter(1) 2.06 15.88 ps
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20 4016 3612 328 284 24 5248440
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Add-in Card Transmitter Test
SIGTEST Results for the 5.0 Gb/s Line RateFigure 16 shows a transition eye diagram, and Figure 17 shows a non-transition eye diagram generated from the SIGTEST application. The SIGTEST results were used only to compare the measurement results from the Agilent PCI Express automated test application. Figure 18 shows the summary of a SIGTEST result.
Total Jitter at BER–12(1) 42.99 68.06 ps
Notes: 1. Without crosstalk.2. In PCI Express mode, the TX_DRIVE_MODE is set to PIPE and the Peak Differential Output
Voltage is programmable by setting TXDEEMPH and TXMARGIN.3. Additional output jitter margin can be gained by using a 125 MHz or 250 MHz reference clock.
This is based on using an external ICS874002AG-02 EVB PCI Express Jitter Attenuator with an onboard ICS874003-05 PCI Express Jitter Attenuator that can be used to convert the 100 MHz reference clock from the PCI Express CBB to 125 MHz or 250 MHz. This PCI Express Jitter Attenuator meets the PLL bandwidth and peaking requirements.
Table 10: Minimum and Maximum Test Results for the 5.0 Gb/s Line Rate (Cont’d)
Test Name Minimum Maximum Units
X-Ref Target - Figure 16
Figure 16: SIGTEST Transition Eye Diagram for the 5.0 Gb/s Line Rate
RPT121_16_061010
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igna
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]
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Add-in Card Transmitter Test
X-Ref Target - Figure 17
Figure 17: SIGTEST Non-Transition Eye Signal Diagram for the 5.0 Gb/s Line Rate
RPT121_17_061410
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]
0.6 0.7 0.8 0.9 1.0 1.1 1.2
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Add-in Card Transmitter Test
X-Ref Target - Figure 18
Figure 18: SIGTEST Result for the 5.0 Gb/s Line Rate
RPT121_18_051410
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Transmitter Differential and Common Mode Return Loss
Transmitter Differential and Common Mode Return Loss
Test MethodologyThe PCI Express Base Specification, Revision 2.1 defines the transmitter differential and common mode return loss as described in Table 11. Differential return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. This output impedance requirement applies to all valid output levels. The reference impedance for differential return loss measurements is 100Ω.
The Agilent 8720ES Vector Network Analyzer (VNA) test equipment used for measuring the transmitter differential and common mode return loss interfaces to a host PC through a GPIB interface. Calibration begins after the measurement parameters are set. These VNA measurements are independent of voltage and are accurate up to 11 GHz. A digital multimeter confirms that the differential resistance is 100Ω before the measurement. Table 12 defines the test setup and conditions. Figure 19 shows the return loss measurement setup.
Table 11: Transmitter Differential and Common Mode Return Loss Specification
Parameter Specification Range Frequency Range Units
TX Differential Return Loss 10 (minimum) From 50 MHz to 1.25 GHz dB
8 (minimum) From 1.25 GHz to 2.50 GHz dB
TX Common Mode Return Loss 6 (minimum) From 50 MHz to 2.50 GHz dB
Table 12: Transmitter Differential and Common Mode Return Loss Test Setup and Conditions
Parameter Value
Measurement Instrument Agilent 8720ES Vector Network Analyzer
TX Coupling / Termination Differential, DC coupled into 50Ω to GND
Voltage Typical Voltage
Temperature Room Temperature
Load Boards ML623 Virtex-6 FPGA GTX Transceiver Characterization Board, Revision C
FPGA Virtex-6 FPGA XC6VLX240T FF1156
Reference Clock Not necessary for this test
Frequency Sweep 50 MHz to 11 GHz (10 MHz steps)
Source Power 0 dBm
Averaging Calibration 1
Intermediate Frequency 100 Hz
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Transmitter Differential and Common Mode Return Loss
Test Results for Transmitter Return LossFigure 20 describes the transmitter differential return loss measurement, and Figure 21 describes the transmitter common mode output return loss measurement. The return loss results are recorded in negative dB.
X-Ref Target - Figure 19
Figure 19: Transmitter Return Loss Test Setup Block Diagram
20 GHz Vector
NetworkAnalyzer
RX - Pair
TX - Pair
GP
IB
port 1
port 2
port 3
port 4
2 Ft. Green Cable 5Vswitch
OFF ON5VDCPlug+
+VCCINT
1V
+VCCO
+VCCAUX
2.5V
2.5V
-GND
50MHz
126
126
122
122
118118
RX0
TX0TX1 RX1116
116
114
114
RX1
TX1
RX0
112RX1
TX1112RX0
TX0
DIFFDIFF
120
120
124
124Socket
FF1156
126
122
118
124
120
116
112
114
+AVTTTX
1.2V
+AVTTRX
1.2V
-GND
+AVCC
1V
+AVCCPLL
1V
PROG DONE
INIT
ACEPC4
SerialGPIBUSB
PCChipScope
Tool
34401ADVM
com
I
V+ GP
IB
ML623
E2
E1
RPT121_19_062810
RX0TX0
RX1TX1
RX1TX1
RX1TX1
TX0
TX0
RX0
TX0RX0
TX1RX1
TX0RX0
RX1
TX1 RX0 TX0 X0Y0
X0Y1
X0Y2
X0Y3
X0Y4
X0Y5
X0Y6
X0Y7
X-Ref Target - Figure 20
Figure 20: Transmitter Differential Return Loss Measurement
RPT121_20_083010
-35.0
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-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Frequency (GHz)
Pow
er (
dB)
PCIe Revision 2.1 Spec
TX Differential ReturnLoss (SSD11)
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PLL Bandwidth Test
PLL Bandwidth Test
Test MethodologyThe PLL Bandwidth test consists of PLL bandwidth and peaking measurements. The PCI Express Base Specification, Revision 2.1 defines the transmitter PLL bandwidth and peaking as described in Table 13 (for the 2.5 Gb/s line rate) and Table 14 (for the 5.0 Gb/s line rate).
This test is performed using the test setup shown in Figure 22. An Agilent J-BERT N4903B Bit Error Rate Tester is used as the clock source, and an Agilent DCA-J 86100C Digital Communication Analyzer with an 86108A Precision Waveform Analyzer is used to perform the PLL Bandwidth test. The Jitter Spectrum Phase Noise (JSPN) application running on an external host PC is used to control the measurement equipment via a GPIB
X-Ref Target - Figure 21
Figure 21: Transmitter Common Mode Return Loss Measurement
RPT121_21_083010
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Frequency (GHz)
Pow
er (
dB) PCIe Revision 2.1 Spec
TX Common ModeReturn Loss (SCC11)
Table 13: PLL Bandwidth Specification for the 2.5 Gb/s Line Rate
Parameter Specification Range Units
PLL Bandwidth From 1.5 to 22 MHz
PLL Peaking 3 (maximum) dB
Table 14: PLL Bandwidth Specification for the 5.0 Gb/s Line Rate
ParameterSpecification
Range ASpecification
Range BUnits
PLL Bandwidth From 5 to 16 From 8 to 16 MHz
PLL Peaking 1 (maximum) 3 (maximum) dB
Notes: 1. Two combinations of PLL bandwidth and peaking are specified for the 5.0 Gb/s line rate to make a
trade-off between the two parameters. If the PLL's minimum bandwidth is ≥ 8 MHz, then up to 3.0 dB of peaking is permitted (Specification Range A). If the PLL's minimum bandwidth is relaxed to ≥ 5 MHz, then a peaking value of up to 1.0 dB must be met (Specification Range B).
2. All transceivers characterized in this report fall within Specification Range A.
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PLL Bandwidth Test
interface. Hardware calibration was completed with the PCIe compliance pattern prior to data collection. The calibration and test procedure methodologies are documented in PCI Express PLL Loop Bandwidth Test Methodology Users Guide, Agilent DCAj 86100C, 86108A Precision Waveform Analyzer, or 83496B Clock Recovery Module, and J-BERT N4903A Bit Error Rate Tester.
The Virtex-6 device under test is configured to transmit the PCI Express compliance pattern on the TX differential lanes on the ML623 board. This device is configured to the default PCI Express mode with the settings described in Table 15. The test setup and conditions for the PLL Bandwidth test are also defined in Table 15.
X-Ref Target - Figure 22
Figure 22: PLL Bandwidth Test Setup Block Diagram
SMA-SMP matched pair cables fromthe PCI Express CBB to the Agilent86100C DCA-J.
SMA-SMP matched pair cables fromAgilent J-BERT N4903B to the PCIExpress CBB.
SMA-SMA matched pair cables fromthe ML623 Characterization Board tothe SMA to PCIe Adapter for the TXlane under test.
SMA-SMA matched pair cables fromthe SMA to PCIe Adapter to the ML623Characterization Board for the 100 MHzreference clock.
DC Blocks
50Ω Termination
RPT121_22_083010
CH1
TX
TXPCLKP
CLKN
TXN
TXP
100 MHz CLKP
100 MHz CLKN
TXN
CH2
Agilent J-BERT N4903B
PCI Express CBBTX RX
CLKIN
CLKINJ
ML623 Characterization Board
Virtex-6XC6VLX240TFF1156 FPGA
TI FusionPowerModule
SMA to PCIeAdapter
DATAP DATAN
Agilent 86100C DCA-J
Agilent 86108A
Table 15: PLL Bandwidth Test Setup and Conditions
Parameter Value
Measurement Instrument
• Agilent J-BERT N4903B.• Agilent DCA-J 86100C Digital Communication Analyzer with 86108A Precision Waveform
Analyzer:• AC coupled using DC blocks.
Software Application
JSPN application:
• Running on an external host PC to control the measurement instrument via GPIB.• PCI-SIG accepted methodology.
Voltage TI Fusion Power Module:
• Installed on the ML623 board to change the MGTAVTT and MGTAVCC voltages between VMIN and VMAX.
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PLL Bandwidth Test
Temperature Temperature Unit:
• A socket attached with a temperature controller is used to change the temperature condition of the device under test between T–40, T0, and T100.
Data Pattern Transmitting the PCI Express compliance pattern on the TX lanes of the ML623 board.
FPGA Virtex-6 FPGA XC6VLX240T FF1156.
Load Boards • ML623 Virtex-6 FPGA GTX Transceiver Characterization Board, Revision C: • 50Ω terminator on TX channels not under test.• On the various ML623 board channels used, there are about 4 to 8 inches of FR4 in the TX paths.
• PCI Express Compliance Base Board (CBB), Revision 2.0:• Standard PCI-SIG board for the Add-in Card Transmitter test.
• SMA to PCIe Adapter, Revision D:• Used to connect the ML623 board to the x16 interface of the PCI Express CBB.
Cables • One pair of matched 50Ω Rosenberger SMA-SMP cables from the PCI Express CBB to the Agilent DCA-J 86100C.
• One pair of matched 50Ω Rosenberger SMA-SMP cables from the Agilent J-BERT N4903B to the PCI Express CBB.
• One pair of matched 50Ω SMA-SMA cables from the SMA to PCIe Adapter to the ML623 board for the 100 MHz reference clock.
• One pair of matched 50Ω SMA-SMA cables from the ML623 board to the SMA to PCIe Adapter for the TX lane under test.
GTX Transceiver Attributes
TX Amplitude and Pre-Emphasis:
• TX_DRIVE_MODE = PIPE• TXDEEMPH = 1'b1• TXSWING = 1'b0• TXMARGIN = 3'b000• TX_DEEMPH_1 = 5'b10010• TX_MARGIN_FULL_0 = 7'b1001101
PLL Charge Pump Configuration:
• TXPLL_CP_CFG = 8'h05• RXPLL_CP_CFG = 8'h05
Reference Clock 100 MHz sourced from the Agilent J-BERT N4903B.
Table 15: PLL Bandwidth Test Setup and Conditions (Cont’d)
Parameter Value
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PLL Bandwidth Test
Test Results for the 2.5 Gb/s Line RateFigure 23 shows the histogram for the PLL bandwidth, and Figure 24 shows the histogram for PLL peaking. All results are measured across process, voltage, and temperature. Figure 25 shows an example of the jitter transfer function of a PLL bandwidth test. Table 16 summarizes the maximum and minimum test result values.X-Ref Target - Figure 23
Figure 23: PLL Bandwidth for the 2.5 Gb/s Line Rate
X-Ref Target - Figure 24
Figure 24: PLL Peaking for the 2.5 Gb/s Line Rate
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5
10
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PLL Bandwidth Test
X-Ref Target - Figure 25
Figure 25: Jitter Transfer Function for the 2.5 Gb/s Line Rate
Table 16: Minimum and Maximum Test Results for the 2.5 Gb/s Line Rate
Test Name Minimum Maximum Units
PLL Bandwidth 4.00 15.00 MHz
PLL Peaking 0.46 1.32 dB
Notes: 1. Hardware calibration with PCIe compliance pattern is performed prior to data collection.2. These results are confirmed with a BERTScope CRJ 125A-PCIE using the PCI-SIG accepted test
procedure documented in PCI Express (Rev2.0) Test Methodology for PLL Loop Bandwidth Response in Add-in cards.
RPT121_25_061010
-40
100E+3 1E+6 10E+6 100E+6
Frequency (Hz)
Mag
nitu
de (
dB)
-35
-30
-25
-20
-15
-10
-5
0
5
10
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PLL Bandwidth Test
Test Results for the 5.0 Gb/s Line RateFigure 26 shows the histogram for the PLL bandwidth, and Figure 27 shows the histogram for PLL peaking. All results are measured across process, voltage, and temperature. Figure 28 shows an example of the jitter transfer function of a PLL bandwidth test. Table 17 summarizes the maximum and minimum test result values.X-Ref Target - Figure 26
Figure 26: PLL Bandwidth for the 5.0 Gb/s Line Rate
X-Ref Target - Figure 27
Figure 27: PLL Peaking for the 5.0 Gb/s Line Rate
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5
10
15
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Receiver Input Jitter Tolerance Test
Receiver Input Jitter Tolerance Test
Test MethodologyThe receiver input jitter tolerance as defined by the PCI Express Base Specification, Revision 2.1 is measured using the test setup shown in Figure 29. The BERTScope BSA125B-PCIE generates a CJTPAT pattern with various components of jitter injected and signal characteristics, as described in Table 18. This table is based on the table labeled “5.0 GT/s Tolerancing Limits for Common Refclk Rx Architecture” in the PCI Express Base Specification, Revision 2.1. Part of the deterministic jitter (DJ), in the form of ISI, is added using 42.42 inches of FR4 through the BERTScope Inter Symbol Interference (ISI) test board.
X-Ref Target - Figure 28
Figure 28: Jitter Transfer Function for the 5.0 Gb/s Line Rate
Table 17: Minimum and Maximum Test Results for the 5.0 Gb/s Line Rate
Test Name Minimum Maximum Units
PLL Bandwidth 5.48 14.00 MHz
PLL Peaking 0.50 0.96 dB
Notes: 1. Hardware calibration with PCIe compliance pattern is performed prior to data collection.2. These results are confirmed with a BERTScope CRJ 125A-PCIE using the PCI-SIG accepted test
procedure documented in PCI Express (Rev2.0) Test Methodology for PLL Loop Bandwidth Response in Add-in cards.
RPT121_28_062810
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100E+3 1E+6 10E+6 100E+6
Frequency (Hz)
Mag
nitu
de (
dB)
-35
-30
-25
-20
-15
-10
-5
0
5
10
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Receiver Input Jitter Tolerance Test
After all of the jitter components listed in Table 18 are added, the resulting eye diagram on the BERTScope is as shown in Figure 30. Sinusoidal jitter (SJ) is swept from 1 kHz to 80 MHz.
X-Ref Target - Figure 29
Figure 29: Receiver Input Jitter Tolerance Test Setup Block Diagram
Connection from the BERTScope SubrateClock to the BERTScope Clock input.
SMA-SMA matched pair cables fromBERTScope Data Out to the ML623Characterization Board for the RXlane under test.
SMA-SMA matched pair cables fromthe ML623 Characterization Board tothe BERTScope Data In for the TX lane.
SMA-SMA matched pair cables fromthe BERTScope Clock output to the ML623 Characterization Board for the 100 MHz reference clock.
DC Blocks 10 dB Attenuator
50 Termination
RPT121_30_083010
TXNTXP
RXP42.42 Inches of FR4
100 MHz CLKN
100 MHz CLKP
RXN
BERTScope ISI Test BoardRX TX
CLKIN
ML623 Characterization Board
Virtex-6XC6VLX240TFF1156 FPGA
TI FusionPowerModule
DATAOUT
CLKOUT
DATAIN
CLK IN
Subrate CLK
BERTScope BSA125B-PCIE
Table 18: Tolerancing Limits for Common Refclk RX Architecture Specification for the 5.0 Gb/s Line Rate
Parameter Specification Limit Units
1.5 to 100 MHz RMS jitter (High Frequency RJ) 3.4 ps RMS
< 1.5 MHz RMS jitter (Low Frequency RJ) 4.2 ps RMS
Maximum DJ impinging on RX under test (High Frequency DJ) 88 ps
33 kHz REFCLK residual (Low Frequency DJ) 75 ps
Minimum single pulse applied at RX(1) 120 ps
Minimum/Maximum pulse voltage ratio(2) 5
Receive eye voltage opening 120 mVPP diff
Common mode noise from RX 300 mVPP
Notes: 1. Calibrated by tuning data output amplitude in BERTScope.2. VPP/Eye Height ratio measured using BERTScope and achieved using 42.42 inches of FR4 through the BERTScope ISI test board.
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Receiver Input Jitter Tolerance Test
The Virtex-6 FPGA GTX transceiver under test recovers the input data and transmits the pattern back to the Data In (Error Detector) of the BERTScope, where bit errors are measured. This is a synchronous test setup with no PPM offset between the BERTScope data generator and the reference clock provided to the Virtex-6 FPGA GTX transceiver under test. Calibration and test are performed based on the methodology described in BERTScopes's PCI Express 5.0 GT/s Add-in Card Receiver Testing documentation. The PCIe Compliance Base Board (CBB) for the add-in card is not used in this setup. The CJTPAT pattern is used because it is a more strenuous test pattern compared to the PCIe compliance test pattern.
Table 19 defines the test setup and conditions for the Receiver Input Jitter Tolerance test.
X-Ref Target - Figure 30
Figure 30: Eye Diagram with Jitter Injected for the 5.0 Gb/s Line Rate
RPT121_29_062910
Table 19: Receiver Input Jitter Tolerance Test Setup and Conditions
Parameter Value
Measurement Instrument
BERTScope BSA125B-PCIE:
• AC coupled using DC blocks.
Voltage TI Fusion Power Module:
• Installed on the ML623 board to change the MGTAVTT and MGTAVCC voltages between VMIN and VMAX.
Temperature Temperature Unit:
• A socket attached with a temperature controller is used to change the temperature condition of the device under test between T–40, T0, and T100.
Data Pattern CJTPAT.
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Receiver Input Jitter Tolerance Test
FPGA Virtex-6 FPGA XC6VLX240T FF1156.
Injected Jitter See Table 18.
BER 10–12 (measured at 10–9, extrapolated to 10–12).
Load Boards • ML623 Virtex-6 FPGA GTX Transceiver Characterization Board, Revision C:• 50Ω terminator on TX channels not under test.• On the various ML623 board channels used, there are about 4 to 10 inches of FR4 in the RX
paths.• BERTScope ISI Test Board:
• With a pair of 10 dB attenuators. • Used to add 42.42 inches of FR4 on the receive path.
Cables • One pair of matched 50Ω SMA-SMA cables BERTScope to the ML623 board for the 100 MHz reference clock.
• One pair of matched 50Ω SMA-SMA cables from the BERTScope to the ML623 board for the RX lane under test.
• One pair of matched 50Ω SMA-SMA cables from the ML623 board to the BERTScope for the forwarded data on the TX lane.
• SMA-SMA connection from the BERTScope Subrate Clock to the BERTScope Clock input for the 100 MHz clock.
GTX Transceiver Attributes
• PLL Charge Pump Configuration:• TXPLL_CP_CFG = 8'h05• RXPLL_CP_CFG = 8'h05
• RX Equalizer:• RXEQMIX = 10'b0000000110
• RX CDR:• PMA_RX_CFG = 25'h05CE008
• DFE:• DFETAP1 = 5'b00000• DFETAP2 = 5'b00000• DFETAP3 = 4'b0000• DFETAP4 = 4'b0000
• RX Termination:• AC_CAP_DIS = FALSE• RCV_TERM_GND = TRUE• RCV_TERM_VTTRX = FALSE
Reference Clock 100 MHz sourced from the BERTScope.
Table 19: Receiver Input Jitter Tolerance Test Setup and Conditions (Cont’d)
Parameter Value
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Receiver Input Jitter Tolerance Test
Test Results for the 5.0 Gb/s Line RateFigure 31 shows the receiver jitter tolerance SJ sweep. Figure 32 shows the minimum receiver sinusoidal jitter tolerance histogram at 22.82 MHz. SJ is applied for each test performed in addition to all the jitter components and amplitude settings defined in Table 18. Table 20 shows the minimum SJ tolerance at 22.82 MHz for the transceivers characterized.X-Ref Target - Figure 31
Figure 31: Receiver Input Jitter Tolerance SJ Sweep for the 5.0 Gb/s Line Rate (CJTPAT, BER = 10–12)
X-Ref Target - Figure 32
Figure 32: Receiver Sinusoidal Jitter Tolerance at 22.8 MHz Test Results (CJTPAT, BER = 10–12)
Table 20: Receiver Input Jitter Tolerance Test Results for the 5.0 Gb/s Line Rate
Parameter Test Condition BERMinimum SJ
ToleranceUnits
Receiver Jitter Tolerance SJ at 22.8 MHz 10–12 0.22 UI
RPT121_31_062810
0.01
1000
0.001 0.01 0.1 1 10 100
SJ Frequency (MHz)
SJ
Am
plitu
de (
UI)
0.1
1
10
100
RPT121_32_062810
0
0.550.50.450.40.350.30.250.20.15
SJ (UI) @ 22.82 MHz
Num
ber
of D
ata
Poi
nts
16
2
4
6
8
10
12
14
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Virtex-6 FPGA GTX Transceiver Report for PCIe 2.0 www.xilinx.com 37RPT121 (v1.0) November 3, 2010
Receiver Differential and Common Mode Return Loss
Receiver Differential and Common Mode Return Loss
Test MethodologyThe PCI Express Base Specification, Revision 2.1 defines the receiver differential and common mode return loss as described in Table 21. Differential return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. This output impedance requirement applies to all valid output levels. The reference impedance for differential return loss measurements is 100Ω.
The Agilent 8720ES VNA test equipment used for measuring the receiver differential and common mode return loss interfaces to a host PC through a GPIB interface. Calibration begins after the measurement parameters are set. These VNA measurements are independent of voltage and are accurate up to 11 GHz. A digital multimeter confirms that the differential resistance is 100Ω before the measurement. Table 22 defines the test setup and conditions. Figure 33 shows the return loss measurement setup.
Table 21: Receiver Differential and Common Mode Return Loss Specification
Parameter Specification Range Frequency Range Units
RX Differential Return Loss 10 (minimum) From 50 MHz to 1.25 GHz dB
8 (minimum) From 1.25 GHz to 2.50 GHz dB
RX Common Mode Return Loss 6 (minimum) From 50 MHz to 2.50 GHz dB
Table 22: Receiver Differential and Common Mode Return Loss Test Setup and Conditions
Parameter Value
Measurement Instrument Agilent 8720ES Vector Network Analyzer
RX Coupling/Termination Differential, DC coupled into 50Ω to GND
Voltage Typical Voltage
Temperature Room Temperature
Load Boards ML623 Virtex-6 FPGA GTX Transceiver Characterization Board, Revision C
FPGA Virtex-6 FPGA XC6VLX240T FF1156
Reference Clock Not necessary for this test
Frequency Sweep 50 MHz to 11 GHz (10 MHz steps)
Source Power 0 dBm
Averaging Calibration 1
Intermediate Frequency 100 Hz
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Receiver Differential and Common Mode Return Loss
Test Results for Receiver Return LossFigure 34 describes the receiver differential return loss measurement, and Figure 35 describes the receiver common mode output return loss measurement. The return loss results are recorded in negative dB.
X-Ref Target - Figure 33
Figure 33: Receiver Return Loss Test Setup Block Diagram
20 GHz Vector
NetworkAnalyzer
RX - Pair
TX - Pair
GP
IB
port 1
port 2
port 3
port 4
2 Ft. Green Cable 5Vswitch
OFF ON5VDCPlug+
+VCCINT
1V
+VCCO
+VCCAUX
2.5V
2.5V
-GND
50MHz
126
126
122
122
118118
RX0
TX0TX1 RX1116
116
114
114
RX1
TX1
RX0
112RX1
TX1112RX0
TX0
DIFFDIFF
120
120
124
124Socket
FF1156
126
122
118
124
120
116
112
114
+AVTTTX
1.2V
+AVTTRX
1.2V
-GND
+AVCC
1V
+AVCCPLL
1V
PROG DONE
INIT
ACEPC4
SerialGPIBUSB
PCChipScope
Tool
34401ADVM
com
I
V+ GP
IB
ML623
E2
E1
RPT121_19_062810
RX0TX0
RX1TX1
RX1TX1
RX1TX1
TX0
TX0
RX0
TX0RX0
TX1RX1
TX0RX0
RX1
TX1 RX0 TX0 X0Y0
X0Y1
X0Y2
X0Y3
X0Y4
X0Y5
X0Y6
X0Y7
X-Ref Target - Figure 34
Figure 34: Receiver Differential Return Loss Measurement
RPT121_34_083010
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Frequency (GHz)
Pow
er (
dB)
PCIe Revision 2.1 Spec
RX Differential ReturnLoss (SDD11)
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Virtex-6 FPGA GTX Transceiver Report for PCIe 2.0 www.xilinx.com 39RPT121 (v1.0) November 3, 2010
Receiver Differential and Common Mode Return Loss
X-Ref Target - Figure 35
Figure 35: Receiver Common Mode Return Loss Measurement
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Frequency (GHz)
Pow
er (
dB)
PCIe Revision 2.1 Spec
RX Common ModeReturn Loss (SCC11)
RPT121_35_083010
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Receiver Differential and Common Mode Return Loss
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Virtex-6 FPGA GTX Transceiver Characterization ReportRevision HistoryTable of ContentsVirtex-6 FPGA GTX Transceiver Characterization Report for the PCI Express 2.0 Electrical StandardIntroductionTest ConditionsTransceiver SelectionSummary of ResultsElectrical Characterization DetailsAdd-in Card Transmitter TestTest MethodologyTest Results for the 2.5 Gb/s Line RateSIGTEST Results for the 2.5 Gb/s Line RateTest Results for the 5.0 Gb/s Line RateSIGTEST Results for the 5.0 Gb/s Line Rate
Transmitter Differential and Common Mode Return LossTest MethodologyTest Results for Transmitter Return Loss
PLL Bandwidth TestTest MethodologyTest Results for the 2.5 Gb/s Line RateTest Results for the 5.0 Gb/s Line Rate
Receiver Input Jitter Tolerance TestTest MethodologyTest Results for the 5.0 Gb/s Line Rate
Receiver Differential and Common Mode Return LossTest MethodologyTest Results for Receiver Return Loss
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