Xilinx CPLDs
Low Cost Solutions At All Voltages
0.35u
CPLD Product PortfolioComplete Solutions for all Markets
0.18u
0.25u
XC9500XL
3.3V5.0 ns tPD
288 mcells
CoolRunner-II
1.8V3.0 ns tPD
512 mcells
XC9500XV
2.5V5.0 ns tPD
288 mcells
XPLA3
3.3V5.0 ns tPD
512 mcells
Lowest Cost 3.3V
Lowest Cost 1.8V
XC9500
5.0V5.0 ns tPD
288 mcells
0.50u
Lowest Power
Low Power
Xilinx CPLD Feature Comparison Feature CoolRunner-II CoolRunner XPLA3 9500XL / XV
Core Voltage 1.8 3.3 3.3 / 2.5Low Power RealDigital + DataGATE Low power mode
Global Clock 3 4 3
P-Term Inputs 40 40 54
Clock ManagementDivide, DualEDGE &
CoolCLOCK None None
I/O StandardsLVTTL, LVCMOS,
HSTL, SSTLLVTTL, LVCMOS LVTTL, LVCMOS
I/O Banks 1 to 4 1 1 to 4 (XV) , 1 (XL)
Macrocells 32-512 32-512 36-288
TPD / FMAX 3.5 / 333 5 / 200 4.0 / 250
Security Multiple levels 1 level 1 level
Process Technology 0.18u 0.35u 0.35u / 0.25u
RealDigital
The RealDigital CPLD
A New Class of CPLD:High Performance & Ultra Low Power
The RealDigital CPLD AdvantageRealDigital Features Benefits
0.18 designwith 100% digital core
High performance up to 385MHz (32mc) Ultra low power of 20uA typical standby, 12mA dynamic (128mc)
with no price premium Scalable for faster technology migration to lower voltage & power
Advanced I/O’s 500mV input hysteresis for improved noise immunity LVTTL, LVCMOS, SSTL, HSTL standards (1.5v to 3.3v capable) DataGATE for lower power consumption
Superior clockmanagement
DualEDGE for increased performance 500MHz toggle rate Clock divide & CoolCLOCK for reduced power consumption
Enhanced security Multiple levels of security for ultimate design protection
Advanced packaging Smallest footprint chip scale High performance BGA with higher I/O per macrocell density
Easy prototyping CoolRunner-II design kit to verify design on known hardware
Single world classsoftware environment
One software system for all Xilinx products Free web download or CD - WebPACK Design fit optimizing - WebFITTER Power estimator - XPower
Features XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512Macrocells 32 64 128 256 384 512FToggle (MHz) 500 454 416 416 416 416
FSYSTEM (MHz) 385 270 263 238 217 217Max I/O 33 64 100 184 240 270
I/O Banks 1 1 2 2 4 4LVCMOS, LVTTL 1.5, 1.8, 2.5, 3.3 Yes Yes Yes Yes Yes Yes
HSTL, SSTL No No Yes Yes Yes YesDualEDGE Yes Yes Yes Yes Yes Yes
DataGATE, CoolCLOCK No No Yes Yes Yes YesStandby Power (uW) 28.8 30.6 34.2 37.8 41.4 45.0
Multiple Levels of Security Yes Yes Yes Yes Yes Yes
Packages (size, type) VQ44 (10 x 10mm, leaded) 33 33 PC44 (16.5 x 16.5mm, leaded) 33 33 CP56 (6 x 6mm, chip scale) 33 45 VQ100 (14 x 14mm, leaded) 64 80 80 CP132 (8 x 8mm, chip scale) 100 106 TQ144 (20 x 20mm, leaded) 100 118 118 PQ208 (28 x 28mm, leaded) 173 173 173 FT256 (17 x 17mm, BGA) 184 212 212 FG324 (23 x 23mm, BGA) 240 270
Maxium User I/O
CoolRunner-II Family Overview
CoolRunner-II FlexibilityXC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512
I/O Banks 1 1 2 2 4 4LVTTL33, LVCMOS
33, 25, 18, 15*SSTL3-1(3.3v), SSTL2-1
(2.5v), HSTL1 (1.5v)Input hysteresis control
Slew rate control
CoolCLOCK
DataGATE
DualEDGE
Clock divider
Bus hold output
Hot pluggable
Note: 1.5v inputs need hysteresis
Programmable Grounds
Design Kit• A complete design kit for:A complete design kit for:
• Logic designers new to CPLDs Logic designers new to CPLDs
• CPLD designers new to XilinxCPLD designers new to Xilinx
• ASIC designersASIC designers
• Simple, inexpensive demo boardSimple, inexpensive demo board• Battery or AC outlet power sourceBattery or AC outlet power source
• Parallel printer cable for programming Parallel printer cable for programming
• LED's for simple testingLED's for simple testing
• Dual in line I/O header for easy connectionsDual in line I/O header for easy connections
• Jumpers for easy modificationsJumpers for easy modifications
• Multiple device selection on a singleMultiple device selection on a single
board (CoolRunner-II or XC9500XL)board (CoolRunner-II or XC9500XL)
• A complete design kit for:A complete design kit for:• Logic designers new to CPLDs Logic designers new to CPLDs
• CPLD designers new to XilinxCPLD designers new to Xilinx
• ASIC designersASIC designers
• Simple, inexpensive demo boardSimple, inexpensive demo board• Battery or AC outlet power sourceBattery or AC outlet power source
• Parallel printer cable for programming Parallel printer cable for programming
• LED's for simple testingLED's for simple testing
• Dual in line I/O header for easy connectionsDual in line I/O header for easy connections
• Jumpers for easy modificationsJumpers for easy modifications
• Multiple device selection on a singleMultiple device selection on a single
board (CoolRunner-II or XC9500XL)board (CoolRunner-II or XC9500XL)
Quick Start Training
• All materials now released!• Full day of training at recent FAE conference• World-wide roll out complete• Set up your customer training now
Quick Start Modules
Module 1: CoolRunner-II Technology & Architecture
Module 2: CoolRunner-II Advanced Features - I
Module 3: CoolRunner-II Advanced Features – II
Module 4: CoolRunner-II In Cell Phone Security
Module 5: Cell Phone Handsets
Module 6: CoolRunner-II in PDAs
Module 7: DDR SDRAM Memory Interface
Module 8: PicoBlaze CPLD Microcontroller
Module 9: Powering CoolRunner-II CPLDs
Module 10: Compact Flash for CoolRunner-II CPLDs
Module 11: CoolRunner-II CPLDs in Security
Module 12: XPower for CoolRunner XPLA3 CPLDs
Module 13: XPower for CoolRunner-II CPLDs
Module 14: CoolRunner-II Low Cost Solutions
Module 15: Digital Camera Design
Module 16: Low Power Memory
Module 17: Smart Card Reader
Module 18: CryptoBlaze
Get up to speed on CoolRunner-II features and new applications
http://www.xilinx.com/products/cpldsolutions/quickstart.htm
Quick Start Modules at:
The CoolRunner XPLA3CPLD Family
Low Power and 3.3V Operation
• Low power, high performance CPLD– 5V tolerant I/O– <100uA standby power– Full JTAG compliance– Industrial temp grade operates from 2.7V
• Ultra-small chip scale packaging– Perfect for portable applications
• Robust architecture delivers great ISP– Superior pin-locking
• WebPACK & ISE software support
CoolRunner XPLA3 - The Lowest Power 3.3V CPLD Solution
The XC9500XL CPLD
High Performance and 3.3V Operation
• I/O Flexibility– XL: 5v tolerant; direct interface to 3.3v & 2.5v
• Input hysteresis on all pins for improved signal integrity• Easy ATE integration for ISP & JTAG
– Fast, concurrent programming times
• 36 to 288 macrocell densities• Complete IEEE 1149.1 JTAG• Space-efficient chip scale packaging
XC9500XL Key Features
XC9500XL Family
Macrocells 36 72 144 288Usable Gates 800 1600 3200 6400tpd (ns) XC9500XL 5 5 5 7.5tpd (ns) XC9500XV 4 5 5 6Registers 36 72 144 288fSYSTEM XC9500XL XC9500XV
178200
178178
178178
125151
Packages PC44 PC44
CS48 CS48
VQ44* VQ44*
VQ64 VQ64
TQ100 TQ100
TQ144 TQ144
CS144 PQ208
BG256
FG256*
CS280*
XC9536XL XC9572XL XC95144XL XC95288XL
Aggressive Cost Management
Cost = Design + Product Cost + COS = Value
I PTASWP D Wafer
Final Test
Assembly
Distribution
Sort Programming
Product Innovation
Inventory
Customer
It’s More Than Just Process and Product Technology Innovation
XC9500
1.8 Volt 3.3 Volt 3.3 Volt 2.5 Volt 5.0 VoltLowest Power Low Power
Highest Performance High PerformanceLowest Cost Lowest Cost
The Complete CPLD Solution
• 1.8 volts to 5 volt operation• Low power/high performance• Low cost
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