1With Insights from: Bill Klein (HPL Linear), Rod Burt (HPL LInear),
Bernd Rundel (HPL DAP), Rick Downs (HPL DAP), Bob Benjamin (HPL DAP)
Selecting the Right Amplifier for a
Precision CDAC SAR A/D
+
-
VIN
A/DDigital
Out?
Tim Green (HPL Linear)
2
Factors of Concern
Power Supply RailsSize of LSBOffsetDrift
NoiseBandwidthDistortionA/D Architecture
Target Example:
+5V, 16-Bit, 100kHz, CDAC, SAR, A/D Application
3
Single Supply
+5V
+3.3V+1.8VSignal ranges:
+1.5V to +5V
Power Supply Rails
Bipolar
+/- 15V Implies: +/-10V signals
4
Signal range is critical +/-10V is a 20V range
12 bits: 20V/4,096 = 4.88mV per LSB 16 bits: 20V/65,536 = 305µV per LSB
+5V range 12 bits: 5V/4,096 = 1.22mV per LSB 16 bits: 5V/65,536 = 76.2µV per LSB 24 bits: 5V/16,777,216 = 298nV per LSB
+3.3V range 12 bits: 3.3V/4,096 = 806µV per LSB 16 bits: 3.3V/65,536 = 50.4µV per LSB 24 bits: 3.3V/16,777,216 = 196nV per LSB
LSB Size
5
DC Parameters If all you have to work with is 38µV (1/2 LSB)…
Offset Voltage becomes significant Offset from differential bias current, too!
OPA335 as an example Single Supply Input offset less than 20µV
Temperature Changes If your system has to operate from -25°C to +75°C, you have a
100°C range of temperature change. If all you have is 38µV (1/2 LSB)…
And 20 µV is used up by offset, then you have 18 µV allowed for drift, so you can handle 180nV/°C of drift
Note: Offset effect may be compensated in the system software!
6
Noise - depends upon bandwidth Resistor noise
1K ohm resistor = 579nV @ 25°C, 20kHz bandwidth. Current noise Voltage noise Sampling Noise of A/D > Tens of μVolts
Distortion THD+N of a 16-bit converter should be better than -98dB, or
0.0011% - again, over the bandwidth of interest. Suitable op amps:
OPA627(Dual Supply) OPA350, OPA134 (Single Supply)
Single Supply Op Amps As common mode voltage changes, op amp passes through
different regions of bias - this results in something similar to crossover distortion
AC Parameters
KTRB4
7
Single Supply RRI Plot - VOS vs CMV
OPA2340 (Dual: VOUT1 & VOUT2 from different halves)
CMV
VOUT1
VOUT2
(Most RRI Op Amps Except OPA363/OPA364)
Gain=X100
Diff Amp Configuration
CH1
CH3
CH2
8
Single Supply RRI Alternate
Avoids CM Input “Crossover”
+
-VIN
A/D
DigitalOut
Inverting “Buffer” Filter
+5V
RB1RB2
RI RF
+5V
0V 0V
+5V
Z IN =
R I
Vnoise
V CM =
+2.
5V
R F =
R I =
1
R B1 =
R B2 =
1
RFLT
CFLT
9
Single Supply Inverting “Buffer”
ZIN is RI (typically < 100kΩ) instead of >100MΩ range
VOUT of Buffer is Inverted from VIN
VCM does not move and is steady at 1/2VCC
Mismatch in ratios of RF / RI = 1 and RB1 / RB2 = 1 Gain & Offset Errors
RI, RF, RB1, RB2 are additional noise sources
10
Input Buffer Selection
Charge injection causes large spike which must settle in tSAMP.
Adding a capacitor (and possibly a resistor) can reduce spike Op amp must be capable of charging capacitance in tSAMP to
0.5LSB. Low output impedance at high frequency required. OPA627 (Dual Supply), OPA350 (Single Supply)
+
-
VIN
VREF
VCC ?1/2VCC ?GND ?
RFLT
CFLT CSH
RSW
SWCONV
20pF-40pF
100
?
?t
V
A/D
SWSAMPL
?
?
11
What Settling Time?
Think of a linear voltage regulator –
There are TWO Settling Times. Line Transient Load Transient
LinearRegulator
+15V +5V
RL
LoadTransient
LineTransient
VINVOUT
12
What Settling Time? Similar to Linear Regulator
Line Transient = Load Transient =
Input Step Voltage; Output Step Voltage;
Output Voltage Slew Rate Output Step Current
+
-
+
-
VINVOUT
CL
IT
LoadTransient
LineTransient
13
Settling Time
Number of bits 0.5LSB Time Constants10 0.0488281% 812 0.0122070% 914 0.0030518% 1116 0.0007629% 1218 0.0001907% 1320 0.0000477% 1522 0.0000119% 1724 0.0000030% 18
14
Op Amp “Line Transient”
Response to change in input signalIncludes Slew Rate.Op Amp data sheets MAY address
Settling Time to 0.01%But we need 0.0007629% for a 16 bit
system
15
“Load Transient” is WORSTWe know the load is the input
capacitance of the A/D (CSH)We do NOT know the starting voltage
on CSH. Possible voltages: GND, Mid-Rail, Random
The Op Amp data sheet does NOT even mention “Load Transient” response.
16
System Design Variables
Op Amp Filter ADC
Noise, Signal BW, Noise Filtering, Acquisition Time,
CMV Range, Slew Rate, Cload Isolation, Architecture (CDAC SAR)
Output Impedance, Settling Time, Charge Bucket Power Supply,
Load Transient, Gain Error, (Flywheel) Data Rate, Resolution,
Power Supply, VOS vs CMV Input, ADC Input, ADC Ref In
Circuit Topology, THD + Noise
+
-
VIN
A/D
DigitalOut
Op Amp Filter
17
SAR A/D < 500kHz
70% Applications Slow Moving “Real World Process” Signals Fast Acquisition & Conversion Allows More System Time For
Processing, Computation, Decision Making Multiplexed, Scanning Systems for Slow Moving Signals
30% Applications AC Fast Moving Dynamic Signals “Real Time” Processing of Input Signals
Assume for our analysis that during sample time VIN is constant
18
Analysis By Example
+
-
VIN
A/DOp Amp Filter
?
+5V
4.87Vpp(65mV to 4.935V Swing)
1kHz
? ?RFLT CFLT
+5V +5V
+VCC+VREF
ADS8320DOUT
19
Analysis Will Use
Tricks
Data Sheet Parameters
Factory Only Parameters
Rules of Thumb
Testing
20
A/D Converter Terms
Acquisition Time (tSMPL): The time the internal A/D sample capacitor is connected to the A/D input.
Conversion Time (tCONV) The additional time the A/D requires to convert the analog input to a
digital output after the acquisition time (tSMPL) is complete.
Throughput Rate [Sampling Rate] Maximum frequency at which A/D conversions can be repeated
i.e. 100kHz Throughput Rate [Sampling Rate] implies that an input analog signal may be converted every 10μs.
21
Standard ADS8320 TimingtSMPL= 4.5 Clk Cycles min
22
A/D tSAMPL Trick
CS/SHDN
System Clock
DCLOCK
Sample
System Clock(SCLCK) DCLOCK tSMPL tCONV tpower down Throughput Rate
2.4MHz System Clock4.5 SCLKs1.87s
16 SCLKs6.67s
3.5 SCLKs1.46s 100kHz
2.4MHz
Modified System Clock fortSMPL = 9 System Clock Cycles
9 SCLKs3.75s
16 SCLKs6.67s
3.5 SCLKs1.46s 84kHz
2x tSAMPL= 84% Throughput Rate
23
ADS8320 Application Specs
“16 Bit, High Speed, 2.7V to +5V, micropower sampling A/D” VCC = +5V, VREF = +5V
Throughput Rate (Sampling Rate) = 100kHz DCLOCK = 2.4MHz, tSAMPL=1.88μs
Input Signal = 4.87VPP (65mV to +4.935V range),1kHz max
SNR = 88dB @ 1kHz THD = -86dB @ 1kHz SINAD = 84dB @1kHz SFDR = 86dB ENOB = 14.33
24
OP Amp Buffer Application Specs
Application: Single Supply = +5V Buffer – NO CM Input Crossover ! Slew Rate to track 1kHz Input Wideband for good gain flatness: 1kHz, G=1 Wideband for fast transient response to Noise Filter Transients Low Noise for 16 Bit performance Fast Settling time for output transients Adequate Output Drive Current for Filter Transients RRIO for 65mV to +4.935V Input and Output on +5V Supply
Best Industry Choice OPA363 or OPA364 (OPA363 with Shutdown feature) “1.8V, 7MHz, 90dB CMRR, Single-Supply, Rail-To-Rail I/O”
25
OPA363/OPA364 Application Specs SRmin (V/μs) = 2 π fVOP (1e-6)
Minimum Slew Rate to track input sinewave (@<1% Distortion?) SRmin = 2∙ π ∙1kHz∙(4.87Vpp/2)∙(1e-6) = 0.015V/μs OPA363/OPA364 = 5V/μs Choose Op Amp SR > 2 X SRmin
Gain Error AVCL = Aol/(1+Aolβ) Aol @1kHz = 80dB = 10000 β = 1 for Unity Gain Follower AVCL= 10,000/(1+10000∙1) = 0.99990001
0.009999% Gain Error @ 1kHz ≈ 12 Bit (1/2 LSB Accuracy) Calibrate gain error at system level Many systems are more concerned about relative changes than absolute
A/D Initial Reference Error (0.02% < Typical Range < 0.2%) Settling Time
OPA363/OPA364: tS = 1.5μs to 0.01%, VS=+5V, G=+1, 4V Step A/D tSAMP = 1.88μs so this looks like a possible good candidate tS to 0.01% < tSAMP
26
OPA363/OPA364 Application Specs
THD+Noise OPA363/OPA364:
THD+N = 0.002%, G=1, RL=2kΩ, VS=5V, f=1kHz, VOUT = 1Vrms 16Bit desired 0.0011%
Open Loop Output Resistance (RO)
OPA363/OPA364: RO = 200Ω
Output Current OPA363/OPA364: IO+ = 40mA,VOUT = +/-0.75V, +/-VS = +/-2.5V
OPA363/OPA364: IO- = 40mA,VOUT = +/-0.5V, +/-VS = +/-2.5V
OPA363/OPA364: IO+ & IO-= 10mA,VOUT = +/-2.25V, +/-VS = +/-2.5V
(continued)
27
Filter Application Specs
RSW = 100Ω (Not needed for Buffer & Filter Calculations)
CSH = 50pF
Worst case ΔV across CSH is VREF
VREF = +5V
tSAMPL = 1.88μs
+
-RSW
CSH
RFLT
CFLT
tSAMPL
28
Charge Transfer Equation: Q = CV
Charge required to charge CSH to VREF
QSH = CSHVREF
QSH = 50pF∙5V = 250pC
IDEAL CFLT (What does CFLT have to be for 1/2 LSB droop on CFLT to change CSH by VREF)
“Charge Bucket” to fill CSH with only a 38μV (1/2LSB) droop on CFLT
QFLT =QSH
QFLT = CFLT (38μV) 250pC = CFLT (38μV) → CFLT = 6.6μF
IDEAL CFLT = 6.6μF Not a good, small, cheap high frequency ceramic capacitor Not practical for Op Amp to drive directly (stability, transient current) Isolation resistor likely not large enough to help isolate Cload and still meet
necessary filter time constant
Filter Application Specs (cont)
29
Filter Application Specs (cont)
Partition the “Charge Bucket” 95% from CFLT
5% from Op Amp
CFLT value required to provide QSH with <5% droop on CFLT
QFLT = QSH
QFLT = CFLT (0.05VREF)
250pC = CFLT (0.05∙5V) → CFLT = 1nF
During tSAMPL the Op Amp must replace 5% VREF on CFLT
Ensure CFLT is at least 10X > CSH
This implies dominant load for Op Amp Buffer is CFLT
1nF = 20 X 50pF CFLT = 20X CSH
30
Filter Application Specs (cont) Time required for CSH & RSW to settle to 1/2LSB @ 16 Bits
RSW = 100Ω (If unknown assume 100 Ω)
τA/D = RSW CSH = 100Ω∙50pF = 5ns
tA/D settle = 12 τA/D = 60ns
Small in comparison to tSAMPL
RFLT Calculation tFLT settle = tSAMPL = 12τFLT
tFLT settle = 1.88μs = 12τFLT
12τFLT = 1.88μs → τFLT = 157ns
τFLT* = 0.60 τFLT
40% Margin for: Op Amp Output Load Transient Op Amp Output Small Signal Settling Time
τFLT* = RFLT CFLT
0.60∙157ns = RFLT 1nF → RFLT =94.2Ω
Use RFLT = 100Ω
31
Op Amp Transient Output Drive to RFLT & CFLT
IOpk max = (5% VREF)/(RFLT) = 250mV/100Ω = 2.5mA
OPA363/OPA364: IO+ & IO- = 2.5mA,VOUT ≈ +/-2.428V, +/-VS = +/-2.5V
VS = +5V Single Supply VOUT = +4.928V
Filter Application Specs (cont)
32
Modified Aol due to RFLT & CFLT
fPX = 1/[(RO + RFLT)CFLT2π] fPX = 1/[(200Ω + 100Ω)1nF∙2π] = 530kHz
fZX = 1/[RFLTCFLT2π] fZX = 1/[100Ω∙1nF∙2π] = 1.6MHz
Stability Check At fcl = 3.2MHz “Rate-of-closure” is
20dB/decade fZX cancels fPX before fcl fPX and fZX are < decade apart
Phase of pole will be cancelled by phase of zero
Buffer Closed Loop Gain Bandwidth fcl = 3.2MHz
VOA BW >2x fcl VOA f-3db = fcl = 3.2MHz VOA BW > 2*fcl = 2*3.2MHz = 6.4MHz OPA364 BW = 7MHz
Op Amp + Filter Analysis – Small Signal
+
-RO
ADS8320
OPA363/OPA364
RFLT
CFLT
1nF
VOAVFLTVfb
33
OP Amp + Filter Analysis – Small Signal (cont)
fcl3.2M
fPX
fZX
AVCL ModifiedAol
34
Log Scale TrickLog Scale Trick (fP = ?):
1) Given: L = 1cm; D = 2cm
2) L/D = Log10(fP)
3) fP = Log10-1(L/D) = 10(L/D)
4) fP = 10(L/D) = 10(1cm/2cm) = 3.16
5) Adjust for the decade range working within – 10Hz-100Hz decade fP = 31.6Hz
6) L = Log10(fp’) X D where fp’ = fp normalized to the 1-10 decade range – fP = 31.6 fP’ = 3.16
0
20
40
60
80
100
10M1M100k10k1k100101
Frequency (Hz)
A (
dB
)
fP = ?
L
D
35
OP Amp + Filter Analysis – Small Signal (cont)
Small Signal Rise Time (10% to 90%) tr = 0.35 / fcl
tr = 0.35 / 3.2MHz = 0.109µs = 109ns
Small Signal Settling Time Constant τsettle ss = 1/(2πfcl)
τsettle SS = 1/(2π∙3.2MHz) = 49.7ns
Small Signal Settling Time tsettle ss = 12τ = (12)(49.7ns) = 596.4ns
Small Signal Transient Response < 40% tSAMPL
ttran ss < 40 % tSAMPL
tr + tsettle SS < (0.40)(tSAMPL)
109ns + 596.4ns < (0.40)(1.8µs) 705.4ns ? < 720ns Close enough to proceed
Small Signal Transient Response
36
OP AMP + Filter Noise Analysis Op Amp + Filter
BW = 1.6MHz Vnoise = (Op Amp Noise)[(Filter BW)(Single Pole Noise BW Ratio)] Vnoise = [17nV/√Hz][√(1.6MHz∙1.57)] = 26.94μVrms
White Noise Dominant with 1.6MHz BW Resistor Noise = √(4KTRB)
B = (Filter BW)(Single Pole Noise BW Ratio) = 1.6MHz∙1.57 = 2.5MHz KT = 4.11x10-21 @ 25°C
100Ω noise = √[4(4.11x10-21)(100 Ω)(2.5MHz)] = 2.03μVrms → Negligible A/D Noise
SNR A/D = 88dB SNR A/D = 20 Log10 (VINrms/Vnoiserms) VIN = 5VPP = 1.7675Vrms A/D Vnoise = 70.365μVrms
System SNR SNR System = 20Log10 [VINrms] / √[(ADC Vnoise)2 + (Vnoise)2] SNR System = 20Log10 [(4.87Vpp/2)(0.707)] / √[(70.365 μVrms)2 + (26.94μVrms)2] SNR System = 87.18dB
ENOB (ideal) = [SNR(dB) – 1.76] / 6.02 ENOB System = [87.18 -1.76] / 6.02 = 14.19
37
ADS8320 On Test System
ADS8320 Data Sheet:
SNR = 88dB
THD = -86dB
SINAD = 84dB
SFDR = 86dB
ENOB = 14.33
38
OPA364, Filter, ADS8320 On Test System
Op Amp+Filter+ADS8320Calculated:
SNR = 87.18dB
ENOB = 14.19
39
Comparison of Tests
ADS8320 Only OPA364, Filter, ADS8320
AD8S320 Data Sheet:
SNR = 88dB
THD = -86dB
SINAD = 84 DB
SFDR = 86dB
ENOB = 14.33
Op Amp+Filter+ADS8320Calculated:
SNR = 87.18dB
ENOB = 14.19
40
Reference Buffer Selection
Reference is DC, right? So a slow op amp is OK? No! Same thing happens on reference input as analog input, but
it must settle in 1 clock cycle! Requirements on reference buffer are even more stringent. Possible Circuit:
41
Promise of more to come…
This is just the beginning Tuning for BEST results
Filter Capacitor AC Magnitude DC Offset Sample Rate
Different converters Testing DC parameters Testing AC parameters Rules of Thumb & Tricks
To Optimize Op Amp, Filter, A/D System
Each Customer WILL NEED TO TEST His/Her Final Application
42
Selecting the Right Amplifier for a
Precision CDAC SAR A/D
Summary of Procedure
43
Summary Steps - CDAC SAR A/D InputBuffer & Filter Selection
+
-
VOA VFLT
VIN
A/DOp Amp Filter
Frequency?Amplitude?
? ?
RFLT CFLT
+VCC +VREF
DOUT
+-Aol x VDIFF
RO VREFCSH
RSW
SWCONV
SWSAMPL
?
BCE
?
DA
44
Buffer / Filter Selection for CDAC SAR A/D Input
1) Specify System Voltages
2) Define maximum input signal Highest Frequency Largest Voltage Swing
3) Choose A/D Converter Select Number of Bits of Resolution Select Maximum Throughput Rate (Sampling Rate) Select Minimum Acquisition Time (tSAMP)
Use DCLOCK stop trick if longer tSAMP is desired
4) Choose CFILT
VREF is max ΔV across CSH
QSH = CSHVREF
QFLT = QSH
QFLT = CFLT(0.05VREF)
Ensure CFLT is at least 10X > CSH
45
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
5) Choose RFILT
tFLT settle = tSAMPL = (#τ)τFLT
(where #τ is number of time constants to reach 1/2LSB settle –
i.e. 12 time constants for settling to ½ LSB for 16Bit A/D) Solve for TFLT
τFLT* = 0.60 τFLT
τFLT* = RFLT CFLT Solve for RFLT
6) Calculate Op Amp Transient Output Drive to RFLT & CFLT
IOpk max = (5% VREF)/(RFLT)
7) Calculate Op Amp Unity Gain Bandwidth First pass select unloaded Op Amp UGBW > 2 X VFLT f-3db
VFLT f-3db = 1/[RFLTCFLT2π]
46
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
8) Op Amp Selection - General Choose Buffer or Inverting Buffer Configuration
If Buffer on Single Supply beware of “Input CMV Crossover”
Slew Rate: SRmin (V/μs) = 2πfVOP (1e-6) Choose Op Amp SR > 2 X SRmin
Gain Error (at the maximum input signal frequency) AVCL = Aol/(1+Aolβ) A/D Initial Reference Error (0.02% < Typical Range < 0.2%)
Settling Time tS to 0.01% < tSAMP
THD+N Close to desired ½ LSB chosen Accuracy
Op Amp Current Drive [IOpk max = (5% VREF)/(RFLT)] Choose for VOPK @ IOpk max
Unity Gain BW: First pass select unloaded Op Amp BW > 4 X VFLT f-3db
Output Resistance (RO) Factory Only Parameter (if not specified in data sheet)
47
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
9) Op Amp Selection – Small Signal Modify Aol due to RFLT & CFLT
fPX = 1/[(RO + RFLT)CFLT2π] fZX = 1/[RFLTCFLT2π]
Stability Check At fcl = 3.2MHz “Rate-of-closure” is 20dB/decade
fZX cancels fPX before fcl fPX and fZX are < decade apart
Phase of pole will be cancelled by phase of zero Buffer Closed Loop Gain Bandwidth = fcl (from modified Aol) VOA BW >2x VFLT BW
VOA f-3db = fcl VFLT f-3db = 1/[RFLTCFLT2π]
Small Signal Transient Response ttran ss < 40 % tSAMPL
tr + tsettle SS < (0.40)(tSAMPL)
τsettle ss = 1/(2πfcl) tsettle ss = (#τ) X τsettle SS
48
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
10) Op Amp + Filter Noise Vnoise = (Op Amp Noise)[(Filter BW)(Single Pole Noise BW Ratio)
Single Pole Noise BW Ratio = 1.57 White Noise Dominant at wide BW
Resistor Noise = √(4KTRB) B = (Filter BW)(Single Pole Noise BW Ratio) Negligible? KT = 4.11x10-21 @ 25°C
11) A/D Noise SNR A/D = 20 Log10 (VINrms/Vnoiserms) Calculate A/D Vnoise
12) System SNR SNR System = 20Log10 [VINrms] / √[(ADC Vnoise)2 + (Vnoise)2] Calculate SNR System
13) System ENOB = [SNR(dB) – 1.76] / 6.02 Calculate System ENOB
14) Prototype & Test Final Configuration
49
Buffer Op Amp RO (Output Resistance)
PartRO
(ohms) PartRo
(ohms) PartRo
(ohms)
OPA132 80 OPA348 600 OPA627 55
OPA227 40 OPA350 50 OPA684 50
OPA277 10 OPA353 44 THS4503 14
OPA300 20 OPA354 35 TLC080 100
OPA335 90 OPA355 40 TLC081 100
OPA336 250 OPA356 30 TLC2272 140
OPA340 80 OPA363 160 TLE2071 80
OPA343 80 OPA380 30 TLV2461 173
50
An Analysis of an Op Amp’s
Open Loop Output Resistance
and
Closed Loop Output Resistance
Appendix - Facts about RO and ROUT
51
Op Amp Model for Derivation of ROUT
+
-
RDIFF
xAol
RO-IN
+IN
-
+
VE
Op Amp Model
1A
VOUT
VO
RF
RI
IOUTVFB
ROUT = VOUT/IOUT
52
= VFB/VOUT = [VOUT (RI / RF + RI)]/VOUT = RI / (RF + RI)
ROUT = VOUT/IOUT
VO = -VE Aol
VE = VOUT [RI/(RF + RI)]
VOUT = VO + IOUTRO
VOUT = -VEAol + IOUTRO
VOUT = -VOUT [RI/(RF + RI)] Aol+ IOUTRO
VOUT + VOUT [RI/(RF + RI)] Aol = IOUTRO
VOUT = IOUTRO / 1+[RIAol/(RF+RI)]
ROUT = VOUT/IOUT =[IOUTRO / 1+[RIAOL/(RF+RI)]]/IOUT
ROUT = RO / (1+Aol)
Derivation of ROUT (Closed Loop Output Resistance)
53
OPA353 Specifications
RO = 40Ω
ROUT (@1MHz, G=10) = 10Ω
Aol @1MHz = 29.54dB = x30
54
OPA353 ROUT Calculation
+
-
RDIFF
xAol
RO-IN
+IN
-
+
VE
Op Amp Model
0.1mA
VOUT
VO
RF
RI
IOUTVFB
ROUT = VOUT/IOUT
1mV
9k
1k
x29.54dBx30
ROUT = 1mV/0.1mAROUT = 10
0.1mV
3mV
+- 4mV
+
-
RO = 40Ω
ROUT (@1MHz, G=10) = 10Ω
Aol @10mHz = 29.54dB = x30
VOUT = IOUTRO / 1+[RIAol/(RF+RI)]
55
ROUT vs RO
RO does not change when feedback is used to close the loop
Closed loop feedback forces VO to increase/decrease
The increase/decrease in VO appears at VOUT as a
reduction in RO
ROUT is the net effect of RO and closed loop feedback controlling VO
56
Op Amp Model for AC Stability Analysis
+
-
+
-
+
-
R1 R2RO
C1 C2
VO
X1X1
X(1X106)
RDIFF
VOUT
200100M
-IN
+IN
VERR
120dBDC open loop gain First Aol Pole
10HzSecond Aol Pole
1MHz
OutputRO = 200
10k
1.59F 15.9pF
10k
AC Small Signal Op Amp Model for Stability Analysis
RF
RI10k
10k
VFB
= VFB / VO
CFILT
RFILT
100
1nF
VFILT
RO is defined as the Op Amp’s Open Loop Output Resistance
RO is measured at IOUT = 0 Amps, f = 1MHz (use the unloaded RO for
AC stability calculations since it will be the largest value which is the worst case for AC stability analysis)
RO is included when calculating for AC Stability Analysis
57
Further Investigation of RO & ZO
For a detailed discussion of RO and ZO refer to:
http://www.analogzone.com/acqt0529.pdf
Operational Amplifier Stability – Part 7 of 15: When Does RO Become ZO?
Bipolar Output Op Amp – Open Loop Output Impedance
Resistive, RO, within unity gain bandwidth of op amp
CMOS RRO Op Amp – Open Loop Output Impedance
Resistive, RO, at high frequencies
Our stability concerns for this technique are at high frequencies
Capacitive, CO, at low frequencies
58
•Zero-Crossover Input Topology•Excellent THD+N: 0.0006% •Excellent CMRR: 100dB •Rail-to-rail input: Input 100mV Beyond Supply Rails •Low noise: 4.5nV/√Hz
•Speed:•Gain bandwidth: 50MHz•Settling time: 300ns to 0.01%
•Low offset: 200µV•2.2V to 5.5V operation
OPA365Zero-Crossover, RRIO, 50MHz Single Supply Amplifier
• Excellent signal linearity over entire input common mode range
• RRIO maximizes input dynamic range with full use of single supply range
• Speed and THD specs optimized for up to 500ksps unity gain buffer data acquisition
OPA365 directly drives single supply ADCs
• Single Supply Data Acquisition • Security & Surveillance• Handheld Test and Measurement • Active Filters• Audio Preamplifiers & Filters• Precision signal conditioning
1k Price:
$0.95
Top Related