VLSI LAB MANUAL
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ANNA UNIVERSITY SYLLABUS EC2357 VLSI DESIGN LAB
1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4
bit multipliers, address decoders, multiplexers), Test bench creation, functional
verification, and concepts of concurrent and sequential execution to be highlighted.
2. Design Entry and simulation of sequential logic circuits (counters, PRBS
generators, accumulators). Test bench creation, functional verification, and concepts
of concurrent and sequential execution to be highlighted.
3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed
in Expt. No. 1 and No. 2 given above. Concepts of FPGA floor plan, critical path,
design gate count, I/O configuration and pin assignment to be taught in this
experiment.
4. Generation of configuration/fuse files for all the blocks/codes developed as
part of Expt.1. and Expt. 2. FPGA devices must be configured and hardware tested
for the blocks/codes developed as part of Expt. 1. and Expt. 2. The correctness of the
inputs and outputs for each of the blocks must be demonstrated at least on
oscilloscopes (logic analyzer preferred).
5. Schematic Entry and SPICE simulation of MOS differential amplifier.
Determination of gain, bandwidth, output impedance and CMRR.
6. Layout of a simple CMOS inverter, parasitic extraction and simulation.
7. Design of a 10 bit number controlled oscillator using standard cell approach,
simulation followed by study of synthesis reports.
8. Automatic layout generation followed by post layout extraction and
simulation of the circuit studied in Expt. No.7
Note 1. For Expt. 1 To 4 can be carried out using Altera (Quartus) / Xilinx
(Alliance) / ACTEL (Libero) tools.
Note 2. For expt. 5-8 introduce the student to basics of IC design. These have to
be carried out using at least 0.5u CMOS technology libraries. The S/W tools needed
Cadence / MAGMA / Tanner.
TOTAL= 45 PERIODS
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CONTENTS
1) Study of Simulation using tools. 2) Design Entry and Simulation of Combinational Logic Circuits
a) Basic logic gates
b) Half adder and full adder
c) Half Subtractor and full Subtractor
d) 8 bit adder
e) 4 bit multiplier
f) Encoder and Decoder
g) Address Decoder
h) Multiplexer
3) Design Entry and Simulation of Sequential Logic Circuits a) Flip-Flops
b) Counter
c) PRBS generator
d) Accumulator
4) Study of Synthesis tools 5) Place and Route and Back annotation for FPGAs 6) Schematic Entry and SPICE Simulation
a) CMOS Inverter
b) Universal Gate
c) Differential Amplifier
7) Layout of a CMOS Inverter 8) Design of a 10 bit number controlled oscillator 9) Automatic Layout Generation
VLSI LAB MANUAL
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VLSI DESIGN
VLSI LAB MANUAL
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ASIC DESIGN FLOW
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Fig 1: Waveform Editor - Initialize Timing Dialog Box
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Expt. No : STUDY OF SIMULATION TOOLS
Date :
AIM:
To study the Simulation tools.
THEORY:
Creating a Test Bench for Simulation:
In this section, you will create a test bench waveform containing
input stimulus you can use to simulate the counter module. This test
bench waveform is a graphical view of a test bench. It is used with a
simulator to verify that the counter design meets both behavioral and
timing design requirements. You will use the Waveform Editor to create a
test bench waveform (TBW) file.
1. Select the counter HDL file in the Sources in Project window.
2. Create a new source by selecting Project - New Source.
3. In the New Source window, select Test Bench Waveform as
the source type, and type test bench in the File Name field.
4. Click Next.
5. The Source File dialog box shows that you are associating the
test bench with the source file: counter.v Click Next.
6. Click Finish. You need to set initial values for your test bench
waveform in the Initialize Timing dialog box before the test
bench waveform editing window opens.
7. Fill in the fields in the Initialize Timing dialog box using
the information below:
Clock Time High: 20 ns.
Clock Time Low: 20 ns.
Input Setup Time: 10 ns.
Output Valid Delay: 10 ns.
VLSI LAB MANUAL
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Initial Offset: 0 ns
Global Signals: GSR (FPGA)
Leave the remaining fields with their default values.
8. Click OK to open the waveform editor. The blue shaded areas are
associated with each input signal and correspond to the Input Setup Time
in the Initialize Timing dialog box. In this tutorial, the input transitions
occur at the edge of the blue cells located under each rising edge of the
CLOCK input.
Fig 2: Waveform Editor - Test Bench
9. In this design, the only stimulus that you will provide is on the
DIRECTION port. Make the transitions as shown below for the
DIRECTION port:
Click on the blue cell at approximately the 300 ns clock transition. The
signal switches to high at this point.
Click on the blue cell at approximately the 900 ns clock transition. The
signal switches back to low.
Click on the blue cell at approximately the 1400 ns clock
transition. The signal switches to high again.
10. Select File - Save to save the waveform. In the Sources in Project
window, the TBW file is automatically added to your project.
11. Close the Waveform Editor window.
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Simulating the Behavioral Model (ISE Simulator):
If you are using ISE Base or Foundation, you can simulate your design with the
ISE Simulator. If you wish to simulate your design with a ModelSim simulator,
skip this section and proceed to the Simulating the Behavioral Model
(ModelSim) section.
Fig 3: Simulator Processes for Test Bench
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Fig 4: Behavioral Simulation in ISE Simulator
To run the integrated simulation processes in ISE:
1. Select the test bench waveform in the Sources in Project window. You can
see the Xilinx ISE Simulator processes in the Processes for Source window.
2. Double-click the Simulate Behavioral Model process. The ISE Simulator
opens and runs the simulation to the end of the test bench.
3. To see your simulation results, select the test bench tab and zoom in on the
transitions. You can use the zoom icons in the waveform view, or right click
and select a zoom command. The ISE window, including the waveform view.
4. Zoom in on the area between 300 ns and 900 ns to verify that the
counter is counting up and down as directed by the stimulus on the
DIRECTION port.
5. Close the waveform view window. You have completed simulation of your
design using the ISE Simulator.
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Simulating the Behavioral Model (ModelSim):
If you have a ModelSim simulator installed, you can simulate your design using
the integrated ModelSim flow. You can run processes from within ISE which
launches the installed ModelSim simulator.
To run the integrated simulation processes in ISE:
1. Select the test bench in the Sources in Project window. You can see
ModelSim Simulator processes in the Processes for Source window in Fig
4.
Fig 5: Simulator Processes for Test Bench
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Fig 6: Behavioral Simulation in ModelSim
2. Double-click the Simulate Behavioral Model process. The ModelSim
simulator opens and runs your simulation to the end of the test bench. The
ModelSim window, including the waveform, should look like
Fig 6.
To see your simulation results, view the Wave window.
1. Right-click in the Wave window and select a zoom command.
2. Zoom in on the area between 300 ns and 900 ns to verify that the
counter is counting up and down as directed by the stimulus on the
DIRECTION port.
3. Close the ModelSim window.
RESULT:
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Design Entry and Simulation of Combinational Logic Circuits Expt. No : BASIC LOGIC GATES
Date :
AIM:
To implement basic logic gates using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above Verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
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PROGRAM: AND Gate:
// Module Name: Andgate
module Andgate (i1, i2,out);
input i1, i2;
output out;
and (out,i1,i2);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1, i2;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Andgate uut1 (.i1(i1),.i2(i2),.out(out));
initial
begin
$display("\t\t\t\tAND Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
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i1=1'b0; i2=1'b0; #1 i2=1'b1;
#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1; #1
$stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Input2 Output
--------------------------------------
0 0 0
0 1 0
1 0 0
1 1 1
--------------------------------------
Simulated Waveform
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PROGRAM OR Gate:
// Module Name: Orgate
module Orgate (i1, i2,out);
input i1, i2;
output out;
or (out,i1,i2);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1, i2;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Orgate uut1 (.i1(i1),.i2(i2),.out(out));
initial
begin
$display("\t\t\t\tORGate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
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i1=1'b0; i2=1'b0; #1 i2=1'b1;
#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1; #1
$stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Input2 Output
--------------------------------------
0 0 0
0 1 1
1 0 1
1 1 1
--------------------------------------
Simulated Waveform
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PROGRAM NOR Gate:
// Module Name: Norgate
Module Norgate (i1, i2,out);
input i1, i2;
output out;
nor (out,i1,i2);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1, i2;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Norgate uut1 (.i1(i1),.i2(i2),.out(out));
initial
begin
$display("\t\t\t\tNORGate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0; #1 i2=1'b1;
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#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1; #1
$stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Input2 Output
--------------------------------------
0 0 1
0 1 0
1 0 0
1 1 0
--------------------------------------
Simulated Waveform
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PROGRAM NAND Gate:
// Module Name: Nandgate
module Nandgate (i1, i2,out);
input i1, i2;
output out;
nand (out,i1,i2);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1, i2;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Nandgate uut1 (.i1(i1),.i2(i2),.out(out));
initial
begin
$display("\t\t\t\tNANDGate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0; #1 i2=1'b1;
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#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1; #1
$stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Input2 Output
--------------------------------------
0 0 1
0 1 1
1 0 1
1 1 0
--------------------------------------
Simulated Waveform
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PROGRAM XOR Gate:
// Module Name: Xorgate
module Xorgate (i1, i2,out);
input i1, i2;
output out;
xor (out,i1,i2);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1, i2;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Xorgate uut1 (.i1(i1),.i2(i2),.out(out));
initial
begin
$display("\t\t\t\tXORGate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0; #1 i2=1'b1;
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#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1; #1
$stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Input2 Output
--------------------------------------
0 0 0
0 1 1
1 0 1
1 1 0
--------------------------------------
Simulated Waveform
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PROGRAM XNOR Gate:
// Module Name: Xnorgate
module Xnorgate (i1, i2,out);
input i1, i2;
output out;
xnor (out,i1,i2);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1, i2;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Xnorgate uut1 (.i1(i1),.i2(i2),.out(out));
initial
begin
$display("\t\t\t\tXNORGate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0; #1 i2=1'b1;
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#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1; #1
$stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Input2 Output
--------------------------------------
0 0 1
0 1 0
1 0 0
1 1 1
--------------------------------------
Simulated Waveform
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PROGRAM NOT Gate:
// Module Name: Notgate
module Notgate (i1, out);
input i1;
output out;
not (out,i1);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Notgate uut1 (.i1(i1),. out(out));
initial
begin
$display("\t\t\t\tNOTGate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b \t\t%b ",i1 ,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0;
#1 i1=1'b1;
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#1 $stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Output
--------------------------------------
0 1
1 0
--------------------------------------
Simulated Waveform
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PROGRAM Buffer:
// Module Name: Buffer
module Buffer (i1, out);
input i1;
output out;
buf (out,i1);
endmodule
// Module Name: Stimulus.v module
module stimulus;
//Inputs
reg i1;
//Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Buffer uut1 (.i1(i1),. out(out));
initial
begin
$display("\t\t\t\tBuffer");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b \t\t%b ",i1 ,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0;
#1 i1=1'b1;
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#1 $stop;
end
endmodule
Symbol
TRUTH TABLE
--------------------------------------
Input1 Output
--------------------------------------
0 0
1 1
--------------------------------------
Simulated Waveform
RESULT:
VLSI LAB MANUAL
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Expt. No: HALF ADDER AND FULL ADDER
Date :
AIM:
To implement half adder and full adder using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
XILINX, ModelSim software.
FPGA kit
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above Verilog code (using ModelSim
or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit
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PROGRAM:
Half Adder:
// Module Name: HalfAddr
module HalfAddr(sum, c_out, i1, i2);
output sum, c_out;
input i1; input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1,i2;
// Outputs
wire sum, c_out;
// Instantiate the Unit Under Test (UUT)
HalfAddr uut (.sum(sum),.c_out(c_out),.i1(i1),.i2(i2));
initial
begin
$display("\t\t\Half Adder");
$display("\t\tInput1\t\t Input2\t\t Carry\t\t Sum");
$display("\t\t----------------------------------------");
$monitor(\%b\t\t%b\t\t%b\t\t,i1,i2,c_out,sum);
$display("\t\t ---------------------------------------);
end
initial
begin
i1=1'b0; i2=1'b0; #1 i2=1'b1;
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#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
LOGIC DIAGRAM: TRUTH TABLE: --------------------------------------------------
Input1 Input2 Sum C_out
---------------------------------------------------
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
----------------------------------------------------
SIMULATED WAVEFORM:
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PROGRAM Full Adder: // Module Name: FullAddr
module FullAddr(i1, i2, c_in, c_out, sum);
input i1, i2, c_in;
output c_out, sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1 , i2 , c_in;
// Outputs
wire c_out, sum;
// Instantiate the Unit Under Test (UUT)
FullAddr uut (.i1(i1),.i2(i2),.c_in(c_in),.c_out(c_out),.sum(sum));
initial
begin
$display("\t\t\t\t\t\tFull Adder");
$display("\t\t----------------------------------------------------------------");
$display("\t\ti1\t\ti2\t\tC_in\t\t\tC_out\t\tSum");
$display("\t\t----------------------------------------------------------------");
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$monitor(" t\t%b\t\t%b\t\t%b\t\t\t%b\t\t%b",i1,i2,c_in,c_out,sum);
#9 $display("\t\t-------------------------------------------------------------------");
end
initial
begin
#1i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 1;
#1 i1 = 0;i2 = 1;c_in = 0;
#1 i1 = 0;i2 = 1;c_in = 1;
#1 i1 = 1;i2 = 0;c_in = 0;
#1 i1 = 1;i2 = 0;c_in = 1;
#1 i1 = 1;i2 = 1;c_in = 0;
#1 i1 = 1;i2 = 1;c_in = 1;
#2 $stop;
end
endmodule
LOGIC DIAGRAM:
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TRUTH TABLE: ----------------------------------------------
Input1 Input2 C_in Sum C_out
--------------------------------------------------
0 0 0 0 0
0 0 1 1 0 \
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SIMULATED WAVEFORM:
RESULT:
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Expt. No: HALF SUBTRACTOR & FULL SUBTRACTOR
Date :
AIM:
To implement half subtractor and full subtractor using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
XILINX, ModelSim software.
FPGA kit
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using ModelSim or
Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
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PROGRAM:
Half Subtractor:
// Module Name: HalfSub
module HalfSub(i0, i1, bor, dif);
input i0, i1;
output bor,
dif;
wire i0n;
not(i0n,i0);
xor(dif,i0,i1);
and(bor,i0n,i1);
endmodule
// Module
Name:Stimulus.v
module Stimulus_v;
// Inputs
reg i0, i1;
// Outputs
wire bor; wire dif;
// Instantiate the Unit Under Test (UUT)
HalfSub uut (.i0(i0),.i1(i1),.bor(bor),.dif(dif));
initial
begin
$display("\t\t\t\t\tHalf Subtractor");
$display("\t\t----------------------------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Borrow\t\t Difference");
$display("\t\t----------------------------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b\t\t%b",i0,i1,bor,dif);
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#4 $display("\t\t-----------------------------------------------------------");
end initial
begin
i0=1'b0; i1=1'b0;
#1 i1=1'b1;
#1 i0=1'b1; i1=1'b0;
#1 i0=1'b1;
i1=1'b1; #1
$stop;
end
endmodule
Logic Diagram:
TRUTH TABLE: --------------------------------------------------
Input1 Input2 bor dif
---------------------------------------------------
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 1
----------------------------------------------------
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SIMULATED WAVEFORM
PROGRAM
Full Subtractor:
// Module Name: FullSub
module FullSub(b_in, i1, i0, b_out, dif); input b_in;
input i1, i0;
output
b_out,dif;
assign {b_out,dif}=i0-i1-b_in;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg b_in, i1,i0;
// Outputs
wire b_out;
wire dif;
// Instantiate the Unit Under Test (UUT)
FullSub uut (.b_in(b_in),.i1(i1),.i0(i0),.b_out(b_out),.dif(dif));
initial
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begin
$display("\t\t\t\t\t\tFull Subtractor");
$display("\t\t-------------------------------------------------------------------------");
$display("\t\tB_in\t\tI1\t\ti0\t\t\tB_out\t\tDifference");
$display("\t\t-------------------------------------------------------------------------");
$monitor("\t\t%b\t\t%b\t\t%b\t\t\t %b\t\t\t %b",b_in,i1,i0,b_out,dif);
#9 $display("\t\t-------------------------------------------------------------------------");
end
initial
begin
// Initialize Inputs
b_in = 0;i1 = 0;i0 = 0;
#1 b_in = 0;i1 = 0;i0 = 0;
#1 b_in = 0;i1 = 0;i0 = 1;
#1 b_in = 0;i1 = 1;i0 = 0;
#1 b_in = 0;i1 = 1;i0 = 1;
#1 b_in = 1;i1 = 0;i0 = 0;
#1 b_in = 1;i1 = 0;i0 = 1;
#1 b_in = 1;i1 = 1;i0 = 0;
#1 b_in = 1;i1 = 1;i0 = 1;
#2 $stop;
end
endmodule
VLSI LAB MANUAL
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LOGIC DIAGRAM:
TRUTH TABLE:
----------------------------------------------
Input1 Input2 C_in Diff Borr
--------------------------------------------------
0 0 0 0 0
0 0 1 1 1 \
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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SIMULATED WAVEFORM:
RESULT:
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Expt. No: 4 BIT MULTIPLIER
Date :
AIM:
To implement four bit multiplier using Verilog.
APPARATUS REQUIRED:
PC with Windows XP
XILINX, ModelSim software
FPGA kit
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 44
PROGRAM
MULTIPLIER
module multi(a,b, c);
input [3:0] a,b;
output [7:0] c;
assign c = a * b;
endmodule
STIMULUS
module testbenchmulti ;
//inputs
reg [3:0] a,b;
//outputs
wire [7:0] c;
multi multipl(.c(c),.a(a),.b(b));
initial
begin
a=4'b0; b=4'b0;
//wait 100ns for global reset to finish
#100; a=4'd3; b=4'd4;
#100; a=4'd3; b=4'd5;
#100; a=4'd2; b=4'd4;
end
endmodule
VLSI LAB MANUAL
Page 45
BLOCK DIAGRAM:
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 46
Expt. No: 8 BIT ADDER
Date :
AIM:
To implement the 8-bit adder using Verilog.
APPARATUS REQUIRED:
PC with Windows XP
XILINX, ModelSim software
FPGA kit
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using ModelSim
or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 47
PROGRAM
8 BIT ADDER
module adder(a,b, s,c);
input [7:0] a,b;
output [7:0] s,c;
assign {c,s} = a + b;
endmodule
STIMULUS:
module testbenadder;
//Inputs
reg [7:0] a,b;
//outputs
wire [7:0] s;
wire c;
adder add(.s(s),.c(c),.a(a),.b(b));
initial
begin
//initialize input
a=8'd0; b=8'd0;
//wait 100ns for global reset to finish
#100; a=8'd1; b=8'd0;
#100; a=8'd9; b=8'd5;
#100; a=8'd5; b=8'd7;
end
endmodule
VLSI LAB MANUAL
Page 48
BLOCK DIAGRAM:
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 49
Expt No: IMPLEMENTATION OF 4x2 ENCODER AND
Date: 2x4 DECODER
AIM:
To implement 4x2 Encoder and 2 x 4 Decoder Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 50
PROGRAM:
Encoder:
// Module Name: Encd2to4
module Encd2to4(i0, i1, i2, i3, out0, out1);
input i0,i1, i2, i3;
output out0, out1;
reg out0,out1;
always@(i0,i1,i2,i3
)
case({i0,i1,i2,i3})
4'b1000:{out0,out1}=2'b00;
4'b0100:{out0,out1}=2'b01;
4'b0010:{out0,out1}=2'b10;
4'b0001:{out0,out1}=2'b11;
default: $display("Invalid");
endcase
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0, i1, i2, i3;
// Outputs
wire out0, out1;
// Instantiate the Unit Under Test (UUT)
Encd2to4 uut(.i0(i0),.i1(i1),.i2(i2),.i3(i3),.out0(out0),.out1(out1));
initial
begin
VLSI LAB MANUAL
Page 51
$display("\t\t 4to2 Encoder");
$display("\t\t------------------------------");
$display("\t\tInput\t\t\tOutput");
$display("\t\t------------------------------");
$monitor("\t\t%B%B%B%B\t\t\t %B%B",i0,i1,i2,i3,out0,out1);
#4 $display("\t\t-------------------------------");
end
initial
begin
i0=1; i1=0; i2=0; i3=0;
#1 i0=0; i1=1; i2=0; i3=0;
#1 i0=0; i1=0; i2=1; i3=0;
#1 i0=0; i1=0; i2=0; i3=1;
#1 $stop;
end
endmodule
BLOCK DIAGRAM:
VLSI LAB MANUAL
Page 52
TRUTH TABLE
Output: 4to2 Encoder
----------------------------------
Input Output
----------------------------------
1000 00
0100 01
0010 10
0001 11
SIMULATED WAVEFORM:
VLSI LAB MANUAL
Page 53
PROGRAM
Decoder:
// Module Name: Decd2to4
module Decd2to4(i0, i1, out0, out1, out2, out3);
input i0, i1;
output out0, out1, out2, out3;
reg
out0,out1,out2,out3;
always@(i0,i1)
case({i0,i1})
2'b00:
{out0,out1,out2,out3}=4'b1000;
2'b01:
{out0,out1,out2,out3}=4'b0100;
2'b10:
{out0,out1,out2,out3}=4'b0010;
2'b11:
{out0,out1,out2,out3}=4'b0001;
default:
$display("Invalid");
endcase
endmodule
VLSI LAB MANUAL
Page 54
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0, i1;
// Outputs
wire out0, out1, out2, out3;
// Instantiate the Unit Under Test (UUT)
Decd2to4 uut (.i0(i0),.i1(i1),.out0(out0),.out1(out1),.out2(out2),.out3(out3));
initial
begin
$display(\t\t 2to4 Decoder);
$display(\t\t --------------------------);
$display(\t\t Input \t\t Output);
$display(\t\t --------------------------);
$monitor(\t\t %b%b\t\t\t %b%b%b %b,i0,i1,out0,out1,out2,out3);
#4 $display(\t\t --------------------------);
end
initial
begin
i0=0;i1=0;
#1 i0=0;i1=1;
#1 i0=1;i1=0;
#1 i0=1;i1=1;
#1 $stop;
end
endmodule
VLSI LAB MANUAL
Page 55
TRUTH
TABLE
Output: 2to4 Decoder
----------------------------------
Input Output
----------------------------------
00 1000
01 0100
02 0010
03 0001
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 56
Expt. No: MULTIPLEXER & DEMULTIPLEXER
Date :
AIM:
To implement Multiplexer & Demultiplexer using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 57
PROGRAM:
Multiplexer:
// Module Name: Mux4to1
module Mux4to1(i0, i1, i2, i3, s0, s1, out);
input i0, i1, i2, i3, s0, s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
VLSI LAB MANUAL
Page 58
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0, i1, i2,,i3, s0, s1;
// Outputs
wire out;
Instantiate the Unit Under Test (UUT)
Mux4to1 uut (.i0(i0),.i1(i1),.i2(i2),.i3(i3),.s0(s0),.s1(s1),.out(out));
initial
begin
$display(\t\t\t4to1 Multiplexer);
$display(\t\t-------------------------);
#1 $display(\t\t\t Input=%b%b%b%b,i0,i1,i2,i3);
$display(\t\t----------------------------------);
$display(\t\tSelector \t\t\t\t Output);
$display(\t\t----------------------------------);
$monitor(\t\t{%b,%b}\t\t\t\t%b,s0,s1,out);
#4 $display(\t\t-----------------------------------------------);
end initial begin
i0=1; i1=0; i2=1; i3=1;
#1 s0=0; s1=0;
#1 s0=1; s1=0;
#1 s0=0; s1=1;
#1 s0=1; s1=1;
#1 $stop;
end
endmodule
VLSI LAB MANUAL
Page 59
LOGIC DIAGRAM:
TRUTH TABLE:
4to1 Multiplexer
--------------------------------
Input = 1011
--------------------------------
Status Output
--------------------------------
{0,0} 1
{0,1} 0
{1,0} 1
{1,1} 1
VLSI LAB MANUAL
Page 60
SIMULATED WAVEFORM:
PROGRAM
Demultiplexer:
// Module Name: Dux1to4
module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in, s0, s1;
output out0, out1, out2,out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule
VLSI LAB MANUAL
Page 61
// Module Name: Stimulus.v
module Stimulus_v;
//Inputs
reg in, s0, s1;
// Outputs
wire out0, out1, out2, out3;
// Instantiate the Unit Under Test (UUT)
Dux1to4 uut (.in(in),.s0(s0),.s1(s1),.out0(out0),.out1(out1),.out2(out2),
.out3(out3));
initial
begin
$display("\t\t 1to4 Demultiplexer");
$display("\t\t------------------------------------");
#1 $display("\t\t\t\tInput=%b",in);
$display("\t\t------------------------------------");
$display("\t\tStatus\t\t\t\tOutput");
$display("\t\t------------------------------------");
$monitor("\t\t{%b,%b}\t\t\t\t%b%b%b%b",s1,s0,out0,out1,out2,out3);
#4 $display("\t\t------------------------------------");
end
initial
begin
in=1;#1 s1=0;s0=0;
#1 s1=0;s0=1; #1 s1=1;s0=0;
#1 s1=1;s0=1; #1 $stop;
end
endmodule
VLSI LAB MANUAL
Page 62
TRUTH TABLE:
1 to 4 Demultiplexer
--------------------------------
Input = 1
--------------------------------
Status Output
--------------------------------
{0,0} 1000
{0,1} 0100
{1,0} 0010
{1,1} 0001
LOGIC DIAGRAM:
VLSI LAB MANUAL
Page 63
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 64
Design Entry and Simulation of Sequential Logic Circuits Expt. No : Flip - Flops
Date :
AIM:
To implement flip flops using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above Verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 65
PROGRAM:
D Flip-Flop:
// Module Name: DFF
module DFF(Clock, Reset, d,
q);
input Clock;
input Reset;
input d; output
q;
reg q;
always@(posedge Clock or negedge
Reset) if (~Reset)
q=1'b0;
else
q=d;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Reset;
reg Clock;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
DFF uut (.Clock(Clock),.Reset(Reset),.d(d),.q(q));
initial
begin
VLSI LAB MANUAL
Page 66
$display("\t\t\t\t\tD FipFlop");
$display("\t\t------------------------------------------------------------");
$display("\t\tClock\t\tReset\t\tInput (d)\t\tOutput q(~q)");
$display("\t\t------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t %d \t\t
%d(%d)",Clock,Reset,d,q,~q);
#15 $display("\t\t------------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0;Reset=0;d=0;
#2 Reset=0;d=1;
#2 d=0;
#2 Reset=1; d=1;
#2 d=0; #2 d=1;
#2 Reset=0; d=0;
#1; // Gap for display.
#2 $stop;
end
endmodule
LOGIC DIAGRAM:
VLSI LAB MANUAL
Page 67
TRUTH TABLE:
D FipFlop
Clock Reset Input (d) Output q(~q)
0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)
SIMULATED WAVEFORM:
VLSI LAB MANUAL
Page 68
T Flip-Flop:
// Module Name: TFF
module TFF(Clock, Reset, t,
q);
input Clock, Reset, t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset)
q=0;
else if (t)
q=~q;
else
q=q;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Clock, Reset, t;
// Outputs
wire q;
// Instantiate the Unit Under Test UUT)
TFF uut (.Clock(Clock),.Reset(Reset),.t(t),.q(q));
initial
begin
$display("\t\t\t\t\tT FipFlop");
$display("\t\t------------------------------------------------------------");
VLSI LAB MANUAL
Page 69
$display("\t\tClock\t\tReset\t\tInput (t)\t\tOutput q(~q)");
$display("\t\t------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t %d \t\t
%d(%d)",Clock,Reset,t,q,~q);
#15 $display("\t\t------------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0; Reset=0;t=0;
#2 Reset=0; t=1;
#2 t=0;
#2 Reset=1; t=1;
#2 t=0;
#2 t=1;
#2 Reset=0; t=0;
#1; // Gap for display.
#2 $stop;
end
endmodule
LOGIC DIAGRAM:
VLSI LAB MANUAL
Page 70
TRUTH TABLE:
Clock Reset Input (t) Output q(~q)
0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 1(0)
0 1 1 1(0)
1 1 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)
SIMULATED WAVEFORM
VLSI LAB MANUAL
Page 71
Program:
JK Flip-Flop:
// Module Name: JKFF
module JKFF(Clock, Reset, j, k, q);
input Clock, Reset, j, k; output q;
reg q;
always@(posedge Clock, negedge Reset)
if(~Reset)
q=0;
else begin
case({j,k})
2'b00: q=q;
2'b01: q=0;
2'b10:
q=1;
2b11: q=~q;
endcase
end
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Clock, Reset, j, k;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
VLSI LAB MANUAL
Page 72
JKFF uut (.Clock(Clock),.Reset(Reset),.j(j),.k(k),.q(q));
initial
begin
$display("\t\t\t\t\tJK FipFlop");
$display("\t\t--------------------------------------------------------------");
$display("\t\tClock\t\tReset\t\tInput (j,k)\t\tOutput q(~q)");
$display("\t\t--------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t (%d,%d) \t\t%d(%d)",Clock,Reset,j,k,q,~q);
#19 $display("\t\t--------------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0; Reset=0;j=0; k=0;
#2 j=0; k=1;
#2 j=1; k=0;
#2 j=1; k=1;
#2 Reset=1;j=0; k=0;
#2 j=0; k=1;
#2 j=1; k=0;
#2 j=1; k=1;
#2 Reset=0; j=0; k=0;
#1; // Gap for display.
#2 $stop;
end
endmodule
VLSI LAB MANUAL
Page 73
LOGIC DIAGRAM:
TRUTH TABLE:
Clock Reset Input (j,k) Output q(~q)
0 0 (0,0) 0(1)
1 0 (0,0) 0(1)
0 0 (0,1) 0(1)
1 0 (0,1) 0(1)
0 0 (1,0) 0(1)
1 0 (1,0) 0(1)
0 0 (1,1) 0(1)
1 0 (1,1) 0(1)
0 1 (0,0) 0(1)
1 1 (0,0) 0(1)
0 1 (0,1) 0(1)
1 1 (0,1) 0(1)
0 1 (1,0) 0(1)
1 1 (1,0) 1(0)
0 1 (1,1) 1(0)
1 1 (1,1) 0(1)
0 0 (0,0) 0(1)
1 0 (0,0) 0(1)
0 0 (0,0) 0(1)
VLSI LAB MANUAL
Page 74
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 75
Expt. No: PRBS GENERATORS
Date :
AIM:
To implement the PRBS generators using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above Verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 76
PROGRAM
PRBS GENERATOR:
module prbs(a,clk,clr);
output [3:0] a;
input clk,clr;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if(clr)
begin
tmp = 4'b1111;
end
else
begin
tmp = { tmp[0]^tmp[1],tmp[3],tmp[2],tmp[1]};
end
end
assign a=tmp;
endmodule
STIMULUS MODULE
module main;
reg clk, reset;
wire rand;
prbs pr (rand, clk, reset);
initial
begin
forever
VLSI LAB MANUAL
Page 77
begin
clk
VLSI LAB MANUAL
Page 78
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 79
Expt. No: ACCUMULATOR
Date :
AIM:
To implement the Accumulator using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above Verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 80
PROGRAM
ACCUMULATOR:
module acc(indata, clk,clr, outdata);
input [3:0] indata;
input clk,clr;
output [3:0] outdata;
reg [3:0] outdata;
always@(posedge clk or posedge clr)
begin
if(clr)
outdata
VLSI LAB MANUAL
Page 81
//output [7:0] outdata;
wire [3:0] outdata;
//Instantiate unit under test (uut)
acc uut (.indata(indata),.clk(clk),.clr(clr),.outdata(outdata));
initial
begin
//Initialize Inputs
indata = 4'd0;
clk = 1'b0;
clr = 1'b1;
#50; indata = 4'd4; clk = 1'b1; clr = 1'b0;
#50; indata = 4'd5; clk = 1'b0; clr = 1'b0;
#50; indata = 4'd3; clk = 1'b1; clr = 1'b0;
#50; indata = 4'd3; clk = 1'b0; clr = 1'b0;
#50; indata = 4'd1; clk = 1'b1; clr = 1'b0;
#50; indata = 4'd7; clk = 1'b0; clr = 1'b0;
#50; indata = 4'd1; clk = 1'b1; clr = 1'b0;
#50; indata = 4'd2; clk = 1'b0; clr = 1'b1;
#50; indata = 4'd9; clk = 1'b1; clr = 1'b0;
end
endmodule
VLSI LAB MANUAL
Page 82
BLOCK DIAGRAM:
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 83
Expt. No: IMPLEMENTATION OF COUNTERS
Date:
AIM:
To implement Counters using Verilog HDL
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above Verilog code (using
ModelSim or Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
VLSI LAB MANUAL
Page 84
PROGRAM:
2- Bit Counter:
// Module Name: Count2Bit
module Count2Bit(Clock, Clear, out);
input Clock, Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge Clear)
if((~Clear) || (out>=4))
out=2'b00;
else
out=out+1;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Clock, Clear;
// Outputs
wire [1:0] out;
// Instantiate the Unit Under Test (UUT)
Count2Bit uut (.Clock(Clock),.Clear(Clear),.out(out));
initial
begin
$display("\t\t\t 2 Bit Counter");
$display("\t\t----------------------------------------");
$display("\t\tClock\t\tClear\t\tOutput[2]");
$display("\t\t----------------------------------------");
$monitor("\t\t %b\t\t %b \t\t %b ",Clock,Clear,out);
VLSI LAB MANUAL
Page 85
#28 $display("\t\t----------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0; Clear=0;
#10 Clear=1;
#18 Clear=0;
#2 $stop;
end
endmodule
LOGIC DIAGRAM:
VLSI LAB MANUAL
Page 86
TRUTH TABLE:
2 Bit Counter
Clock Clear Output[2]
0 0 00
1 0 00
0 0 00
1 0 00
0 0 00
1 0 00
0 0 00
1 0 00
0 0 00
1 0 00
0 1 00
1 1 01
0 1 01
1 1 10
0 1 10
1 1 11
0 1 11
1 1 00
0 1 00
1 1 01
0 1 01
1 1 10
0 1 10
1 1 11
0 1 11
VLSI LAB MANUAL
Page 87
SIMULATED WAVEFORM:
RESULT:
VLSI LAB MANUAL
Page 88
Expt No: STUDY OF SYNTHESIS TOOLS
Date:
AIM:
To study the synthesis tool.
THEORY:
Now that you have created the source files, verified the design behavior
with simulation, and added constraints, you are ready to synthesize and
implement the design.
Implementing the Design:
1. Select the counter source file in the Sources in Project window.
2. In the Processes for Source window, click the + sign next to
Implement Design. The Translate, Map, and Place & Route processes are
displayed. Expand those processes as well by clicking on the + sign. You
can see that there are many sub-processes and options that can be run
during design implementation.
3. Double-click the top level Implement Design process.ISE determines
the current state of your design and runs the processes needed to pull your
design through implementation. In this case, ISE runs the Translate, Map
and PAR processes. Your design is now pulled through to a placed-and-
routed state. This feature is called the pull through model.
4. After the processes have finished running, notice the status markers in
the Processes for Source window. You should see green checkmarks next to
several of the processes, indicating that they ran successfully. If there are
any yellow exclamation points, check the warnings in the Console tab or
the Warnings tab within the Transcript window. If a red X appears next to a
process, you must locate and fix the error before you can continue.
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Figure 7: Floor planner View - Detailed View
Figure 8: Design Summary View