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University at SUNY Buffalo
Student of Engineering
Department of Electrical Engineering
Design and Simulation of Two-stage Op-Amp
Self Study
Instructor: Dr. Praveen Meduri
Buffalo, NY, USA
Prepared by
Jianfeng Sun
ID: 37068562
Electrical Engineering
12/08/2015
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Contributions
This is a self-study report that based on knowledge from course EE 491.
The main goal of this experiment is to design and simulate the circuit of two-stage op-amp in
order to meet the requirements that the instructor has offered.
My task is to first design the circuit from the parameters of the TSMC025 model of the transistors
and the specifications by hand calculation then using the software of Cadence to simulate the
circuit in order to meet the requirements.
The relationship between this report and my knowledge from the course EE 491 is that in the EE
491 class, by using the information that I have learned of the circuits of the MOSFET such as the
single stage amplifier, current mirror, differential amplifier, current source and deep triode
resistors stand by MOSFET, etc. Then combined all of these parts to construct a two-stage op-
amp in order to satisfy the specifications. In other words, the knowledge that I have learned from
the EE 491 class is the fundamental towards to the analysis of the IC design.
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Summary
The main purpose of the report to verification of the results either from the hand calculation or
from the simulation of the software Cadence to meet the specifications that given by the
instructor.
The major points covered in this reports are the graphs of voltage gain, GBW, phase margin, slewrate, ICMR, and OVSR and using these result to check whether the specifications are meet or not.
The major conclusions in this report is that almost all of the value of the requirements are meet,
but for the ICMR and OVSR, the actual values are kind of with a little deviation, but they are still
correct.
The major recommendations in this report are the reference given by the instructors, textbooks
and online source.
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Table of ContentsContributions ................................................................................................................................... 2
Summary ......................................................................................................................................... 3
List of Figures ................................................................................................................................. 5 List of Tables ................................................................................................................................... 6 1 Introduction............................................................................................................................. 7 2
Results .................................................................................................................................... 8
2.1 Hand Calculation ............................................................................................................. 8
2.2 Circuit Schematic ............................................................................................................ 9 2.3 AC Analysis .................................................................................................................... 9 2.4 ICMR ............................................................................................................................. 10 2.5
OVSR ( Range of Vout ) ................................................................................................. 11 2.6 Slew Rate ....................................................................................................................... 12
2.7 Pdiss ................................................................................................................................. 13 2.8 MOSEK ......................................................................................................................... 13
Engineering Analysis .................................................................................................................... 16
Conclusion ..................................................................................................................................... 16 References ..................................................................................................................................... 16
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List of Figures
Figure 1.1 - 1 Design specifications ................................................................................................ 7
Figure 2.2 - 1 Two stage amplifier circuit lay out ........................................................................... 9 Figure 2.3 - 1 Ac analysis of AV, margin phase and GB ................................................................ 9Figure 2.4 - 1 Circuit used to calculate ICMR .............................................................................. 10
Figure 2.4 - 2 DC response of ICMR ............................................................................................ 10
Figure 2.5 - 1 Circuit used to calculate the range of output voltage .............................................. 11
Figure 2.5 - 2 DC response of range of output voltage ................................................................. 11Figure 2.6 - 1 Circuit used to calculate slew rate .......................................................................... 12Figure 2.6 - 2 Slew rate of two stage amplifier ............................................................................. 12
Figure 2.7 - 1 Pdiss of the two stage amplifier .............................................................................. 13
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List of Tables
Table 1.1 - 1 Design specifications ................................................................................................. 7
Table 2.3 - 1 AC analysis of the circuit ........................................................................................... 9 Table 2.4 - 1 DC response of ICMR.............................................................................................. 10
Table 2.5 - 1 Value of OVSR ........................................................................................................ 11
Table 2.6 - 1 Value of Slew Rate .................................................................................................. 12
Table 2.7 - 1 Value of Pdiss ............................................................................................................. 13
Table 3 - 1 Summary of simulation ............................................................................................... 16
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1 Introduction
In this project, we used the TSMC025 model for transistors of NMOS and PMOS to build a two
stage op amp in order to meet the special design specifications as following:
Table 1.1 - 1 Design specifications
Phase margin 60o
AV >7500V/V
VDD 3.3V
VSS 0V
GB 10MHz
SR >10V/us
OVSR 0.4V to 2.9V
ICMR 1V to 2V
Pdiss
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2 Results
2.1 Hand Calculation
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2.2 Circuit Schematic
Figure 2.2 - 1 Two stage amplifier circuit lay out
2.3 AC Analysis
Figure 2.3 - 1 Ac analysis of AV, margin phase and GB
Table 2.3 - 1 AC analysis of the circuit
Parameters Specifications Simulation results
AV >7500 V/V (77.5 dB) 78.83 dB
Margin phase 60o 60.28o
GB 10MHz 10.01MHz
It is obvious that all three values of parameters from simulation are very close to the expected
values. So that the results from simulation are matched with the specification values.
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2.4 ICMR
Figure 2.4 - 1 Circuit used to calculate ICMR
Figure 2.4 - 2 DC response of ICMR
Table 2.4 - 1 DC response of ICMRParameter Specification Result from simulation
ICMR 1V to 2V 28.82mV to 2.6V
The highest value is very close to the requirement, I had try my best to increase the lowest value
of ICMR to approach 1V, but the most possible number that I can got is 28.8186 mV.
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2.5 OVSR ( Range of Vout )
Figure 2.5 - 1 Circuit used to calculate the range of output voltage
Figure 2.5 - 2 DC response of range of output voltage
Table 2.5 - 1 Value of OVSR
Parameter Specification Result from simulation
OVSR 0.4V to 2.9V 3.65mV to 2.99V
Same as ICMR, the highest value of OVSR is satisfied, but the lower boundary is so hard to be
completed.
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2.6 Slew Rate
Figure 2.6 - 1 Circuit used to calculate slew rate
Figure 2.6 - 2 Slew rate of two stage amplifier
The slew rate is the average value of the two slopes (positive and negative) of the two lines.
Slope1: (2.2366-0.99665) V/ (1.1001-1.1802) us=-15.48 V/µs
Slope2: (1.9798-0.69547) V/ (1.8648-1.7649) us= 12.86 V/µs
Average slew rate: 14.17 V/µs
Table 2.6 - 1 Value of Slew Rate
Parameter Specification Result from simulation
SR >10 V/µs 14.17 V/µs
So that the result from simulation matches with the specification value for SR.
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2.7 Pdiss
Figure 2.7 - 1 Pdiss of the two stage amplifier
Table 2.7 - 1 Value of Pdiss
Parameters Specification Result from simulation
Pdiss
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AV:
GB:
Slew rate:
Pdiss:
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ICMR:
OVSR:
Size of transistors:
Phase margin:
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Engineering Analysis
Table 3 - 1 Summary of simulationParameters Specifications Results
Phase margin 60o 60.28o
AV >77.5 dB 78.83dB
GB 10MHz 10.01MHzSR >10V/us 14.17 V/µs
OVSR 0.4V to 2.9V 3.65mV to 2.99V ICMR 1V to 2V 28.82mV to 2.6V
Pdiss
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