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2012-1634
(Reexamination No. 95/001,134)
IN THE
UNITED
STATES
COURT OF
APPEALS
FOR THE FEDERAL CIRCUIT
RAMBUS, INC.,
Appellant,
v.
David J. Kappos, DIRECTOR,
UNITED STATES PATENT AND TRADEMARK OFFICE,Appellee,
and
NVIDIA CORPORATION,
Appellee.
Appeal from the United States Patent and Trademark Office,
Board of Patent Appeals and Interferences.
BRIEF FOR RAMBUS INC.
November 28, 2012
J. Michael Jakes
James R. Barney
Molly R. Silfen
FINNEGAN,HENDERSON,FARABOW,
GARRETT &DUNNER,LLP
901 New York Avenue, NW
Washington, DC 20001
(202) 408-4000
Attorneys for Appellant Rambus Inc.
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CERTIFICATE OF INTEREST
Pursuant to Federal Circuit Rules 27(a)(7) and 47.4(a), counsel for Appellant
Rambus Inc. certify the following:
1. The full name of every party or amicus represented by us is:
Rambus Inc.
2. The name of the real party in interest (if the party named in the caption is not
the real party in interest) represented by us is:
Rambus Inc.
3. All parent corporations and any publicly held companies that own 10 percent or
more of the stock of any party represented by us are:
None
4. The names of all law firms and the partners or associates that appeared for the
parties now represented by us in the trial court or are expected to appear in this
Court are:
J. Michael Jakes, James R. Barney, Molly R. Silfen
FINNEGAN,HENDERSON,FARABOW,GARRETT &DUNNER, LLP
Paul M. Anderson
Paul M. Anderson, PLLC
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TABLE OF CONTENTS
Table of Authorities ...................................................................................................vStatement of Related Cases .................................................................................... viiiStatement of Jurisdiction ............................................................................................1I. Statement of the Issues ....................................................................................2II. Statement of the Case ......................................................................................3III. Statement of Facts ............................................................................................5
A. Background ...........................................................................................51. Dynamic Random Access Memory Devices ..............................52. Asynchronous Versus Synchronous Memory
Devices ........................................................................................73. Transition-Based Control Signals Versus
Read/Write Requests ...................................................................94. Using Both Edges of a Clock Signal to Transfer Data .............14
B. The 097 Patent ...................................................................................151. Relation to the Farmwald Family of Patents ............................152. Claims-at-Issue ..........................................................................153. Evidence Relating to the Meaning of External Clock
Signal .......................................................................................164. Evidence Relating to the Meaning of Write
Request ....................................................................................21C. The Inagaki Anticipation Rejection ....................................................24
1. Inagaki Discloses an Asynchronous System ............................242. The Examiner and Board Found the External Clock
Signal Limitation Satisfied by the Intermittent,
Nonperiodic Signal of Inagaki ..................................................27
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3. Despite This Courts Construction Requiring aSeries of Bits, the Examiner and the Board
Nevertheless Found Write Request to Be Satisfied
by Inagakis Conventional, Transition-Based Signals..............30D. The iAPX Obviousness Rejection .......................................................33
1. iAPX Does Not Disclose a Double Data Rate, and ItUses Both Edges of Its Clock Signals for Other
Purposes ....................................................................................332. The Examiner Erroneously Believed iAPX Does Not
Use Both Edges of Its Clock Signals for Other
Purposes ....................................................................................353. Despite iAPXs Use of Both Edges of Its Clock
Signals for Other Purposes, and Despite the
Examiners Failure to Recognize This Fact in His
Rejection, the Board Nevertheless Concluded that It
Would Have Been Obvious to Modify iAPX to
Perform the Double-Data-Rate Technique of Inagaki ..............364. The Board Dismissed the Objective Evidence of
Nonobviousness ........................................................................40IV. Summary of Argument ..................................................................................44V. Argument .......................................................................................................45
A. Standard of Review .............................................................................45B. The Board Erred in Implicitly Construing External Clock
Signal to Include Intermittent, Nonperiodic Signals .........................46C. The Board Erred in Disregarding This Courts Prior
Construction of Write Request and in Construing Write
Request to Include Conventional, Transition-Based
Control Signals ....................................................................................51D. After the Examiner Made a Clear Factual Error Regarding
the Teaching of iAPX, the Board Erred in Affirming the
Examiners Obviousness Rejection on Alternative Grounds ..............56
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E. The Boards Construction of Memory Device IsErroneous .............................................................................................64
VI. Conclusion .....................................................................................................64
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TABLE OF AUTHORITIES
Page(s)
CASES
Alcon Research, Ltd. v. Apotex Inc.,687 F.3d 1362 (Fed. Cir. 2012) . ........................................................................ 62
Arkie Lures, Inc. v. Gene Larew Tackle, Inc.,
119 F.3d 953 (Fed. Cir. 1997) ........................................................................... 63
Becton, Dickinson & Co. v. Tyco Healthcare Group,
616 F.3d 1249 (Fed. Cir. 2010) ......................................................................... 49
Biovail Corp. International v. Andrx Pharmaceuticals, Inc.,
239 F.3d 1297 (Fed. Cir. 2001) ......................................................................... 48
Gambro Lundia AB v. Baxter Healthcare Corp.,
110 F.3d 1573 (Fed. Cir. 1997) ......................................................................... 63
Hynix Semiconductor Inc. v. Rambus Inc.,
645 F.3d 1336 (Fed. Cir. 2011) ......................................................................... 52
In re Baker Hughes Inc.,
215 F.3d 1297 (Fed. Cir. 2000) . ........................................................................ 45
In re Cyclobenzaprine Hydrochloride Extended-Release CapsulePatent Litigation,
676 F.3d 1063 (Fed. Cir. 2012) . .................................................................. 59, 60
In re Fritch,
972 F.2d 1260 (Fed. Cir. 1992) ......................................................................... 58
In re Glatt Air Techniques, Inc.,
630 F.3d 1026 (Fed. Cir. 2011) . ........................................................................ 62
In re Gordon,733 F.2d 900 (Fed. Cir. 1984) ........................................................................... 58
In re ICON Health & Fitness, Inc.,
496 F.3d 1374 (Fed. Cir. 2007) ......................................................................... 45
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vi
In re Kao,
639 F.3d 1057 (Fed. Cir. 2011) . .................................................................. 58, 62
In re Lee,
277 F.3d 1338 (Fed. Cir. 2002) ......................................................................... 59
In re Nouvel,
No. 2011-1526, 2012 WL 3716769 (Fed. Cir. Aug. 29, 2012) ......................... 59
In re NTP, Inc.,
654 F.3d 1279 (Fed. Cir. 2011) ......................................................................... 45
In re Rambus Inc.,
694 F.3d 42 (Fed. Cir. 2012) ....................................................................... 52, 64
In re Ratti,270 F.2d 810 (CCPA 1959) ............................................................................... 58
In re Suitco Surface, Inc.,
603 F.3d 1255 (Fed. Cir. 2010) . ........................................................................ 45
In re Zurko,
258 F.3d 1379 (Fed. Cir. 2001) ......................................................................... 59
Intel Corp. v. Broadcom Corp.,
172 F.Supp.2d 478 (D. Del. 2001) ..................................................................... 54
Karlin Technology Inc. v. Surgical Dynamics, Inc.,
177 F.3d 968 (Fed. Cir. 1999) ........................................................................... 54
Kinetic Concepts, Inc. v. Smith & Nephew, Inc.,
688 F.3d 1342 (Fed. Cir. 2012) ................................................................... 52, 60
Markman v. Westview Instruments, Inc.,
517 U.S. 370 (1996) ........................................................................................... 54
Metabolite Laboratories, Inc. v. Laboratory Corp. of America Holdings,370 F.3d 1354 (Fed. Cir. 2004) ......................................................................... 63
Miken Composites, L.L.C. v. Wilson Sporting Goods Co.,
515 F.3d 1331 (Fed. Cir. 2008) ......................................................................... 53
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Mintz v. Dietz & Watson, Inc.,
679 F.3d 1372 (Fed. Cir. 2012) ......................................................................... 60
Rambus Inc. v. Infineon Technologies AG,
318 F.3d 1081 (Fed. Cir. 2003) ..................................................................passim
St. Clair Intellectual Property Consultants, Inc. v. Canon Inc.,
412 F. Appx 270 (Fed. Cir. 2011) ............................................................... 48, 49
Star Scientific, Inc. v. R.J. Reynolds Tobacco Co.,
655 F.3d 1364 (Fed. Cir. 2011) ......................................................................... 63
Tec Air, Inc. v. Denso Manufacturing Michigan Inc.,
192 F.3d 1353 (Fed. Cir. 1999) ................................................................... 57, 58
Therasense, Inc. v. Becton, Dickinson & Co.,593 F.3d 1325 (Fed. Cir. 2010) ......................................................................... 61
Trading Technologies International, Inc. v. eSpeed, Inc.,
595 F.3d 1340 (Fed. Cir. 2010) ................................................................... 50, 51
USA Choice Internet Services, LLC v. United States,
522 F.3d 1332 (Fed. Cir. 2008) ......................................................................... 49
STATUTES
35 U.S.C. 134(b) ...................................................................................................... 1
35 U.S.C. 141 ........................................................................................................... 1
35 U.S.C. 311-314.................................................................................................. 1
35 U.S.C. 315(a)(1) .................................................................................................. 1
OTHER AUTHORITIES
WEBSTERS NINTH NEW COLLEGIATE DICTIONARY 1160 (1986) ............................. 54
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STATEMENT OF RELATED CASES
Rambus is unaware of any other appeals or petitions taken in this
reexamination proceeding. There are, however, a number of different matters
pending in this Court and other courts that involve the patent-at-issue in this
appeal, U.S. Patent No. 6,260,097 (the 097 patent).
1. The following pending cases involve the 097 patent.
a. Rambus Inc. v. Hynix Semiconductor Inc., No. 5:05-cv-00334-
RMW (N.D. Cal.) (Whyte, J.).
b. Rambus Inc. v. LSI Corp., No. 3:10-cv-05446-RS (N.D. Cal.)
(Seeborg, J.).
c. Rambus Inc. v. Micron Technology Inc., No. 5:06-cv-00244-
RMW (N.D. Cal.) (Whyte, J.).
d. Rambus Inc. v. STMicroElectronics, N.V., No. 3:10-cv-05437-
RS (N.D. Cal.) (Seeborg, J.).
2. The following pending cases do not involve the 097 patent but
involve patents that, like the 097 patent, descend from Application No.
07/510,898 (the 898 application).
a. Hynix Semiconductor Inc. v. Rambus Inc., No. 5:00-cv-20905-
RMW (N.D. Cal.) (Whyte, J.). This case is on remand from Appeal Nos. 2009-
1299, -1347, 645 F.3d 1336 (Fed. Cir. 2011).
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b. Micron Technology v. Rambus Inc., No. 1:00-cv-00792-SLR
(D. Del.) (Robinson, J.). This case is on remand from Appeal No. 2009-1263,
645 F.3d 1311 (Fed. Cir. 2011).
3. Several ex parte and inter partes reexaminations involving patents
descended from the 898 application are pending at the U.S. Patent and Trademark
Office (PTO). Of those, the following case was decided by this Court.
a. In re Rambus Inc., No. 2011-1247 (Fed. Cir. decided Aug. 15,
2012).
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STATEMENT OF JURISDICTION
This appeal arises from an inter partes reexamination proceeding before the
U.S. Patent and Trademark Office (PTO). See 35 U.S.C. 311-314. Rambus,
the patent owner, appealed the examiners final rejection of the claims to the Board
of Patent Appeals and Interferences (Board), which had jurisdiction under
35 U.S.C. 134(b) and 315(a)(1). The Board issued a final decision affirming the
rejection on June 11, 2012, and Rambus appealed. This Court has jurisdiction
under 35 U.S.C. 141.
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I. STATEMENT OF THE ISSUES1. In finding that Inagaki discloses a synchronous memory device in
which data transfer is synchronized with an external clock signal, did the Board
err by implicitly construing external clock signal to include an intermittent,
nonperiodic signal that is incapable of governing the timing of responses to
transaction requests on the busi.e., the undisputed hallmark of a synchronous
memory system?
2. In finding that Inagaki discloses a write request, did the Board err by
ignoring this Courts prior construction of write request, which requires a series
of bits, and then alternatively reasoning that even if claim 1 somehow requires a
series of bits, the series can be a series of one bit, contrary to the ordinary
meaning of series?
3. In affirming obviousness based on iAPX in view of Inagaki, did the
Board err by: (1) incorrectly construing memory device; (2) substituting its own
conjecture in place of clear evidence that the dual-edge/double-data-rate feature of
Inagaki could not be combined with iAPX because iAPX already uses both edges
of its clock signals for other purposes; and (3) improperly discounting the objective
evidence of nonobviousness?
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II. STATEMENT OF THE CASERambus appeals the Boards rejection of claims 1-5, 7, 26, 28-32, 34, and 35
of U.S. Patent No. 6,260,097 (the 097 patent).1
First, the Board erred in
rejecting claims 1, 2, and 7 as being anticipated by Japanese Patent Publication JP
57-210495 to Inagaki (Inagaki). Inagaki does not disclose a synchronous
memory device having an external clock signal as those terms are used in the
097 patent. Instead, Inagaki discloses an asynchronous memory system in which
data is transferred according to an intermittent signal that is present only during
data transfer. Inagakis intermittent signal cannot be used to govern the timing of
responses to transaction requests on the bus because this requires an external clock
that runs independently of data transfer. Thus, in sustaining this rejection, the
Board implicitly and improperly broadened the meaning of external clock signal
to include nonperiodic signals that do not meet the agreed-upon definition of a
synchronous memory device, which requires an external clock signal which
governs the timing of the response to [a] transaction request. A1067-68
(emphasis added).
The drawings below show the difference between an external clock signal as
disclosed in the 097 patent (top), and the intermittent, nonperiodic signal disclosed
in Inagaki (bottom):
1Rambus does not appeal claims 8, 10-12, and 14.
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Note that the external clock signal (top) runs periodically at all times, whereas the
nonperiodic Inagaki signal runs only intermittently (during data transfer), making it
useless as an external clock.
The Boards Inagaki rejection is also erroneous because Inagaki does not
issue a write request as that term is properly construed. In a related case, this
Court construed write request to mean a series of bits used to request a write of
data to a memory device. Rambus Inc. v. Infineon Techs. AG, 318 F.3d 1081,
1093 (Fed. Cir. 2003) (Infineon). Inagaki, in contrast, does not issue a series of
bits but, instead, uses a conventional transition-based signal to initiate a write
operation. In a transition-based system, read/write operations are initiated by
driving the voltage on a particular bus line either high or low (i.e., causing a
voltage transition), which does not constitute transmitting any bits, let alone a
series of bits as required by this Courts construction. As a fallback, the Board
asserted that, even if claim 1 somehow requires a series of bits, the series can be a
series of one bit. A13-14 & n.7. This rationale fails, however, because the
ordinary meaning of series requires more than one bit.
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The Board also erred in rejecting claims 1-5, 7, 26, 28-32, 34, and 35 as
obvious over two iAPX references (iAPX Manual (A2968-3221) and iAPX
Electrical Specifications (A3238-345) (collectively iAPX)) in view of Inagaki.2
In doing so, the Board incorrectly construed memory device and ignored clear
evidence that the iAPX system is incompatible with using both edges of a timing
reference for data transfer because both edges of the iAPX clock signals are
already used for other purposes. The Board tacitly acknowledged that the
examiner got this wrong but nevertheless affirmed the examiner on different
grounds, hypothesizing various other ways in which iAPX allegedly might have
worked if it had been designed differently. In short, the Board substituted its own
conjecture for the undisputed facts, and it compounded this error by improperly
discounting Rambuss objective evidence of nonobviousness.
III. STATEMENT OF FACTSA. Background
1. Dynamic Random Access Memory DevicesDynamic random access memory devices, or DRAMs, store information
in memory cells, which are typically arranged in a two-dimensional rectangular
2The examiner also applied U.S. Patent No. 4,480,307 (Budde, A3222-37) in
view of Inagaki. A1119-57. That reference, however, describes the same system
as the iAPX documents (A1156-57; A1643), and the Board declined to address
Budde separately from iAPX (A33). Accordingly, all arguments presented herein
with respect to iAPX apply equally to Budde.
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array. A58[1:60-64]; A1766[15]. The array includes columns and rows, such
that each cell can be accessed using a row/column address. A58[1:60-64];
A1766[15]. Each memory cell contains a capacitor for storing a charge
representing one bit of information; for example, a charged capacitor may
represent a 1, while a capacitor with no charge would represent a 0.
A58[1:60-64]; A1766[15]. A computer typically has many DRAMs controlled by
a single memory controller.
A central processing unit can transfer information to or from a memory cell
using the memory controller. A1766-67[13-20]. The memory controller
accesses a designated row/column address in a given DRAM and performs either a
read or write operation. Id. To read information, the memory controller sends
instructions to sense the charge on the capacitor in that cell. To write information,
the memory controller sends instructions to change the charge on the capacitor in
that cell to represent either a 0 or a 1. Id.
Information and control signals flowing to and from the numerous DRAMs
can travel on a bus, consisting of a series of wires or lines that connect the
DRAMs to the memory controller. A59[3:52-4:35]. A major focus of the 097
patent is to make the memory system more efficient so that data can be transferred
faster than was possible in the prior art. A60[5:29-32]. This is accomplished, in
part, by: (1) employing a synchronous memory interface, i.e., one that utilizes an
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external clock signal to govern memory transactions on the bus; (2) using multi-bit
read/write requests that enable pre-scheduling and interleaving of data transfers,
in contrast to prior-art systems that could only support one operation at a time
using transition-based signals; and (3) employing a double-data-rate technique that
uses both edges of a clock signal to transfer data. These features will be discussed
in more detail below.
2. Asynchronous Versus Synchronous MemoryDevices
Prior to 1990 (the effective filing date of the 097 patent), conventional
DRAMs operated asynchronously, i.e., without being synchronized with an
external clock signal. A1767[20]; A58[2:45-48]. Read and write operations were
conducted as soon as the memory controller requested them and the DRAMs were
able to respond. A1767[20]. This was considered the most efficient way to
access information because each DRAM transferred data as soon as possible after
receiving a request for that data. See A2640.
In contrast, the DRAMs disclosed in the 097 patent are synchronous
memory devices. A41. The hallmark of a synchronous memory device is that an
external clock signal governs the timing of the read and write operations for all
DRAMs on the bus. A1767-68[21]; A59[3:9-12]. In a synchronous memory
system, at least one signal line carries an external clock signal, such as the one
shown below, which is used (either directly or indirectly) to synchronize all read
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and write operations for all the DRAMs in the system. A61[8:28-29]; A1767-
68[21]; see A61[8:42-57]; A56.
In this manner, the memory controller and its DRAMs operate synchronously
with each other. For instance, the memory controller can issue a read request to a
particular DRAM and specify that the requested data must be returned in a precise
number of clock cycles. A1767-69[21-27]. Then, after that precise number of
clock cycles has elapsed, that DRAM responds and the controller can check the
data on the bus line and know that it is the data associated with the earlier read
request. Id. Meanwhile, in the intervening clock cycles, the memory controller
can issue another request to another DRAM and start that process while the first
DRAM is working to process the first read request. Id. In this way, transactions
can be interleaved and pre-scheduled to occur at certain times, i.e., after a certain
number of clock cycles. Id.
To understand why interleaving and pre-scheduling are desirable, it is
important to remember that read and write operations take time and that a memory
bus has only a limited number of lines to carry all the necessary control signals and
data between the memory controller and multiple DRAMs. Id. If the bus lines are
tied up during a particular transaction with one DRAM, they are not available for
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other transactions the memory controller may wish to execute with other DRAMs
at that time. With pre-scheduling, however, during the intervening clock cycles
between when a particular request is issued and when the data is returned in
response to that request, the memory controller can issue other requests or pick up
data from previous requests. Id. This ability to interleave transactions increases
the overall efficiency of the system. Id.
The key to a synchronous memory system is an external clock that provides
a continuous, periodic signal on the bus that the controller and all memory devices
on the bus can reference at all times, irrespective of whether they happen to be
actively transferring data. Id.; A1807-09[9-12]. This allows the timing of all
read/write transactions on the bus to be precisely coordinated by the controller.
3. Transition-Based Control Signals VersusRead/Write Requests
Prior-art asynchronous DRAMs used transition-based control signals to
perform read and write operations. A1767-69[21-27]. In a transition-based
system, the memory controller asserts a control signal by driving the voltage on
one of the control lines on the bus from high to low, or vice versa. Id.
Conventional asynchronous DRAMs accomplished reading and writing using a
RAS/CAS interface, where RAS stands for Row Address Strobe and CAS
stands for Column Address Strobe. A1767[20]; A59[3:20-22]. Specifically,
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RAS and CAS are both transition-based control signals. Below is an illustration of
a typical asynchronous RAS/CAS system:
A1713.
In the RAS/CAS system shown above, when information at a particular
memory cell (row/column) is to be read, the controller first transmits the row
address on the ADDRESS line and drives the voltage on the RAS line low, as
shown above. A60[5:64-6:5]; A1767-69[21-27]. The voltage transition on the
RAS line tells the DRAM that a particular row corresponding to the address needs
to be accessed. A1767-69[21-27]. The DRAM responds by activating the
specified row, making it ready for the read operation. Id. Next, the controller
transmits a column address on the ADDRESS line and drives the voltage on the
CAS line low, as shown above. Id. This tells the DRAM that the column
corresponding to the address needs to be accessed. Once the desired row and
column have been identified in this manner, the DRAM transmits the binary data
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corresponding to the capacitor charge at that address onto the DATA lines, as
shown above. If desired, another column address can be identified in that same
row (as shown above) and data can be read from that second location in the same
manner. Id. Finally, when the RAS line is driven high again (as shown above), the
row is deactivated. Id.
Notably, during the entire duration of a read or write operation in an
asynchronous memory device, both the RAS and CAS signal lines, as well as the
write-enable (WE) line, are tied up and unavailable for other transactions. Id. This
can be seen in the example above, where all of the control lines are tied up during
the entire read operation. Because of this, any other read/write transactions
between the memory controller and other DRAMs on the bus must wait until the
previous operation is fully completed. Id. In very high-speed systems, this is a
serious drawback. A1769[26]; A2615; A2617; A2620-21; A2639; A2089-
90[28-36]. The 097 inventors solved this problem by abandoning conventional
transition-based controls and instead utilizing multi-bit read requests and write
requests in conjunction with a synchronous memory system.
In the context of a synchronous memory system, a read or write request is a
series of bits that is sent to the memory device to indicate that a particular read or
write operation is desired. A1768[24]. Unlike with transition-based (e.g.,
RAS/CAS) controls, a read or write request can be used to pre-schedule the data
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transfer associated with a particular read/write operation, so that it will only occur
after a certain number of clock cycles have elapsed. A1767-68[21]; A61[7:7-16].
Such precise scheduling is enabled by the presence of an external clock signal,
which continues cycling in periodic intervals independently of the DRAM itself
and regardless of whether the DRAM is transferring data. A1767-69[21-27]. In
this way, allDRAMs on the bus can be synchronized with the controller, and data
transfers can be precisely scheduled to occur in the future. Id. Note that this
would not be possible if the external clock were started and stopped with each
individual data transfer of each DRAM on the bus.
A simple example of a write request in a synchronous system is shown
below:
A1714.
In this example, the CLOCK line carries a continuously periodic signal that
governs all the read and write operations for all the DRAMs on the bus. A write
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request for a particular DRAM is issued on the REQUEST line3
and is sampled
(i.e., captured) by that DRAM in association with the rising edge of the clock
signal. See A1767-69[21-27]. At the same time, a designated address
(row/column) is transmitted on the ADDRESS line and is also sampled by the
DRAM. Notably, the requested data to be written to that DRAM is not provided
on the DATA line until two clock cycles later. This is because the write operation
has been pre-scheduled to begin two clock cycles after receipt of the write
request. Id. During the intervening period, the external clock signal on the bus
continues cycling in a periodic manner, which allows the controller to know
precisely when to provide the appropriate data to be written to the DRAM (i.e.,
after two clock cycles in this example). This is the essence of the pre-scheduling
feature mentioned above, which is a major advantage of the 097 patents
synchronous memory system over prior-art asynchronous systems. Id. This
feature depends on the external clock signal being periodic and continuously
present on the bus for use as a timing reference before, during, and after each
individual read/write request and its associated data transfer. Id.
The advantage of the pre-scheduling protocol is somewhat
counterintuitive. Although the synchronous memory device may have to wait
3Although the figure above shows a single line, the boxes actually represent more
than one bit of data and are therefore transmitted on multiple lines simultaneously.
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longer than prior-art asynchronous devices to perform each individual read or write
operation, efficiency is gained overall because the intervening clock cycles can
now be used for additional requests, such as requests to other memory devices,
without the lines being tied up throughout the duration of each request. A61[7:7-
13]; A1768[24]. This can be seen in the example above, where the REQUEST
and ADDRESS lines immediately become free again as soon as the write request is
issued, even though that transaction is not yet complete. As the 097 inventors
realized, this modification greatly increases the overall efficiency of data storage
and retrieval. A1768[22].
4. Using Both Edges of a Clock Signal to Transfer DataEach cycle of a clock signal can be said to have a rising edge (where the
voltage rises) and a falling edge (where the voltage drops). A1769[25]. In prior-
art memory systems such as iAPX, a conventional protocol was to use only one
edge of a clock signal (e.g., the rising edge) to trigger the transfer of each bit of
data. A1811-13[22-28]. The 097 inventors, however, disclosed a more
efficient system that uses both the rising and falling edges of the clock signal for
transmitting information, in combination with a high-speed synchronous memory
system. Id.; A67[19:35-46]; A68-69[22:53-23:29]; A1767-69[21,25]. This
technique doubles the rate at which data can be stored or retrieved without having
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to speed up the clock signal itself, which can introduce potential errors at the very
high speeds enabled by synchronous DRAMs. A67[19:35-46]; A2092[50].
B. The 097 Patent1. Relation to the Farmwald Family of Patents
The 097 patent claims priority to Application No. 07/510,898 (the 898
application), filed on April 18, 1990. A41. The 898 application led to a large
family of Farmwald patents, including the 097 patent and U.S. Patent Nos.
6,564,281 (the 281 patent), 6,584,037 (the 037 patent), and 6,034,918
(the 918 patent). A41; A4189; A4239; A4272. All of these Farmwald patents
share a substantially identical specification. See A41-71; A4189-303.
2. Claims-at-IssueClaims 1-5, 7, 26, 28-32, 34, and 35 of the 097 patent are at issue in this
appeal. Representative claim 1 recites as follows:
1. A method of controlling a synchronous memory
device, wherein the memory device includes a plurality
of memory cells, the method of controlling the memory
device comprises:
issuing a write requestto the memory device, wherein in
response to the write request, the memory device samples
first and second portions of data;
providing a first portion of data to the memory device
synchronously with respect to a rising edge transition of
an external clock signal; and
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providing a second portion of data to the memory device
synchronously with respect to a falling edge transition of
the external clock signal.
A69-70[24:61-25:6] (emphasis added). Of particular interest here are the proper
constructions for external clock signal and write request in the context of a
synchronous memory device.
3. Evidence Relating to the Meaning of External ClockSignal
The 097 claims are directed to a method of controlling a synchronous
memory device that transfers data synchronously with respect to . . . an external
clock signal. The specification describes such external clock signals and how
they are used to create a device clock, the true system clock. A67[19:1]; see
A66-67[18:65-19:1]; A68-69[22:53-23:29]. As shown in Figure 13 of the 097
patent, the external clock, or in that example the two external clocks that are
combined to create the true system clock, are continuously periodic. A55. The
same can also be seen on the CLOCK line in Figure 14, reproduced below. A56.
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For the system to be able to keep time with respect to an external clock
signal, and for the device to be able to wait a selected number of clock cycles
after the memory controller has issued a read or write request, the clock must
continue cycling in a predictable, periodic way, even during periods when data is
not actively being transferred. See A1768[24] (explaining that requests in a
synchronous memory device are sampled at a particular moment in time based on
the clock signal). In particular, the specification explains that the system relies on
such an external clock signal to interleave requests, such that one DRAM can be
working on a first request while a different DRAM works on a second request:
Each slave [e.g., DRAM] on the bus must decode the
request packet to see if that slave needs to respond to the
packet. The slave that the packet is directed to must then
begin any internal processes needed to carry out the
requested bus transaction at the requested time. The
requesting master may also need to transact certain
internal processes before the bus transaction begins.After
a specified access time the slave(s) respond by returning
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one or more bytes (8 bits) of data or by storing
information made available from the bus. More than one
access time can be provided to allow different types of
responses to occur at different times.
A request packet and the corresponding bus access areseparated by a selected number of bus cycles [i.e., clock
cycles], allowing the bus to be used in the intervening
bus cycles by the same or other masters for additional
requests or brief bus accesses. Thus multiple,
independent accesses are permitted, allowing maximum
utilization of the bus for transfer of short blocks of data.
A60-61[6:62-7:13] (emphasis added); see also A61[8:47-51] ([A] slave [i.e.,
DRAM] should preferably respond to a request in a specified time, sufficient to
allow the slave to begin or possibly complete . . . any internal actions that must
precede the subsequent bus access phase.).
In other words, the memory controller issues a request to a particular
DRAM, waits a specified number of clock cycles, and then reads or writes the
requested information. A60-61[6:62-7:13]. Meanwhile, the memory controller
can issue a request to a second DRAM while the first DRAM is working on
responding to the first request. Id. The only way for the memory controller to
know which requests response it is receiving is by knowing the precise number of
clock cycles that have passed since each request was issued. Similarly, in order for
the memory devices themselves to know when to respond, they need to have
access to this same clock information. This, in turn, requires an external clock that
continues cycling in a periodic manner throughout all of these operations, i.e.,
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before, during, and after each individual request and associated data transfer. Id.;
see A62[9:10-11].
The specification similarly explains that all the devices on the bus must be
synchronized according to one clock signal (A61[8:28-29]), which means that the
clock must be active even when one or more of those devices are inactive. In this
manner, all devices can act in a coordinated manner because [t]he time for [the]
bus access phase is known to all devices on the bus. A61[8:52-53]. A specific
parameter therefore preferably indicates the timing of the response to a read or
write request. A62[9:56-57]; see A62[10:9-11] (explaining that default response
time is preferably eight clock cycles). Thus, as shown throughout the
specification, the device of the 097 patent requires an external clock signal that
allows the memory controller to coordinate the timing of multiple interleaved
read/write requests on the bus.
Obviously, for the system to be able to wait a specified number of clock
cycles and for the memory controller to access other DRAMs in the intervening
time, those clock cycles must occur predictably. A1807-09[9-12]. If the clock
signal stopped cycling, the system would simply wait forever, with outstanding
requests never completed because they were scheduled for a return on a later cycle.
Id. The specification therefore requires that the external clock signal be
continuously periodic, regardless of whether a particular memory device is actively
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transferring data at a particular time. Put differently, the external clock must
continue cycling periodically in the background, independent of any particular
data-transfer operation of any individual DRAM on the bus.
Throughout prosecution of the Farmwald family of patents, the applicants
and the PTO consistently treated the claimed external clock signal as a
continuously periodic signal. For example, in responding to a rejection during
prosecution of the Farmwald 281 patent, Rambus explained that even though the
applied prior-art reference referred to certain signals as clock signals, those did
not correspond to the claimed external clock signal of the application because
they were not predictably periodic such that they could be used to orchestrate
timing events on the bus. A2700 n.2. Specifically, the examiner had applied a
reference that referred to prior-art RAS and CAS signals as input clock signals.
Id. In response, Rambus argued that the asynchronous strobe signals employed in
the conventional DRAMs, namely RAS and CAS, are not [the] external clock
signal(s) described in the Farmwald patents: In this regard, notwithstanding the
[prior arts] reference to RAS and CAS signals as input clock signals, the
external clock signal of the instant application is a periodic signal used to
orchestrate timing events. Id. (citation omitted).
Likewise, the same examiner who reexamined the 097 patent applied the
Farmwald 037 patent as prior art in a different proceeding and stated that the
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clock signal disclosed in the Farmwald patents is always present. A2713-14;
A2739-40; see also A1737. Specifically, the examiner explained that while the
clock signal [in the Farmwald patent] indicates when data can be sampled[,] the
signal itself does not trigger the sampling of data upon receipt of that clock signal
since the clock signal is always present. A2714 (emphasis added); see A2740
([T]he clock signal itself is always present hence it does not cause a delay to
occur until it is received.).
4. Evidence Relating to the Meaning of Write RequestThe appealed claims all require issuing a write request to the memory
device. The 097 specification explains that a write request (or read request) is
part of a larger transmission called a request packet. A61-62[8:58-9:5]
(explaining that a request packet is a contiguous series of bytes containing
address and control information).
An example of a request packet is illustrated in Figure 4 of the 097 patent:
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A46. As the specification explains, a request packet contains both address bytes
and control bytes. A62[9:23-25]. In Figure 4 above, the address bytes are
labeled as ADDRESS, and the control bytes consist of the remaining fields,
i.e., ACCESSTYPE, MASTER, and BLOCKSIZE. See also A62[9:23-25].
In the 097 patent, the notation [a:b] refers to bits of data transferred on the bus
lines. Thus, AccessType[0:3] refers to four bits labeled 0 through 3, which are
each carried on a different bus line. The control bytes section is further
explained (in relevant part) as follows:
The first byte contains two 4 bit fields containing
control information, AccessType[0:3], an op code
(operation code) which, for example, specifies the type of
access, and Master [0:3], a position reserved for the
master sending the packet to include its master ID
number. . . .
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The AccessType field specifies whether the requested
operation is a read or write and the type of access, for
example, whether it is to the control registers or other
parts of the device, such as memory. . . .
AccessType[1:3] provides up to 8 different access types
for a slave. AccessType[1:2] preferably indicates the
timing of the response, which is stored in an access-time
register, AccessRegN. . . . The remaining bit,
AccessType[3] may be used to send additional
information about the request to the slaves.
A62[9:38-64].
Thus, a read or write request may include all of the information contained in
the first byte of the control bytes section, as explained above. A62[10:23-30].
At a minimum, this includes the type of access requested (i.e., whether the
operation is a write or read) and the mode (i.e., whether access will be in page
mode, normal mode, etc.). See, e.g.,A62[10:20-23].
This Court has previously addressed the meaning of write request in
another Farmwald patent (the 918 patent) having a common specification with the
097 patent. InInfineon, this Court construed write request to mean a series of
bits used to request a write of data to a memory device. 318 F.3d at 1093. The
Court relied on the language of the specification, as explained above. Id. at 1092-
93. Specifically, the Court discussed the analogous read request and noted that
the specification states that it contains the four-bit AccessType field and specifies
what type of read (e.g., page mode, normal mode, etc.) to perform. Id. The
Court therefore construed read request to mean a series of bits used to request a
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read of data from a memory device where the request identifies what type of read
to perform. Id. at 1093. The Court construed write request analogously to
mean a series of bits used to request a write of data to a memory device. Id.
C. The Inagaki Anticipation Rejection1. Inagaki Discloses an Asynchronous System
Inagaki is a Japanese reference that discloses a conventional asynchronous
memory system circa 1981, with transition-based control signals. A1809[14];
A1792[116]; A2945-67. Inagaki claims to have improved over conventional
asynchronous memory devices by transferring data at twice the conventional
speed by using both the rise and fall of its intermittent pulsed signal. A2955.
Inagaki discloses several irregular, nonperiodic signals that are asserted only
during periods of data transfer. Specifically, Inagakis many signals are shown
below.
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A2961. The first line in the drawing above represents a CE, or chip enable,
signal, which causes an address to be accessed when the voltage on that line is
driven high. A2955-56. The address to be accessed is sent along the ADD line.
Id. Like the conventional transition-based RAS and CAS signals described above,
signals , 1, 2, and 31-34 in Inagaki (albeit labeled clocks) are asserted only
when data output or input is to occur, i.e., intermittently, in nonperiodic fashion.
A1793[118]. Specifically, when data output or input is to occur, signal is
toggled, and signals 1 and 2 are then derived from both the rise and fall of the
signal, resulting in signals 1 and 2. A2956; A1793[118]. Inagaki discloses that
signals 1 and 2 cause a shift register to shift, which then allows data to be
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output or input. A2956. When Inagaki does not intend to output or input any data,
signal and its derivative signals 1 and 2 are not toggled.
Inagaki describes signals , 1, and 2 as clocks. But Inagaki uses the
term clock synonymously with signal, not referring to continuously periodic
clock signals. Indeed, Inagaki uses clock to refer to many of its signals,
including ones that are clearly nonperiodic, like the chip enable ([CE]) signal
shown above, which is driven high when data output and input are to be performed
and remains high throughout the entire process. A2955 (describing the chip enable
signal as a first clock [CE]); A1793[120]; A1809[15]. Likewise, Inagaki calls
the prior-art CAS signal, which is asserted intermittently, a clock. A2958.
All of the control signals in Inagaki are transition-based signals that do not
send or receive information in the form of bits but, instead, convey only a
transition from high to low voltage or vice versa. A1794[122]. Moreover,
Inagaki need not and does not provide an external clock signal that governs the
timing of responses to read/write requests on the bus. A1792-94[116-24];
A1809-10[13-20]. It need not provide such an external clock signal because
each read/write request is processed one at a time, without interleaving or pre-
scheduling, as was typical of prior-art asynchronous memory systems circa 1981.
This is very different from the synchronous memory system disclosed and claimed
in the 097 patent.
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2. The Examiner and Board Found the External ClockSignal Limitation Satisfied by the Intermittent,
Nonperiodic Signal of Inagaki
The examiner correctly construed synchronous memory device as a
memory device that receives an external clock signal which governs the timing of
the response to [a] transaction request. A1067-68 (emphasis added) (quoting
Murphy Declaration at A1809[14]); see also A1044 (citing district court decision
at A2534-37). Thus, it is undisputed that an external clock signal in the claims-
at-issue must govern the timing of the response to a transaction request. The 097
patent explains this timing concept as follows:
The bus uses a relatively simple, synchronous, split-
transaction, block-oriented protocol for bus transactions.
One of the goals of the system is to keep the intelligence
concentrated in the masters, thus keeping the slaves [i.e.,
the DRAMs] as simple as possible (since there are
typically many more slaves than masters). To reduce the
complexity of the slaves, a slave should preferablyrespond to a request in a specified time, sufficient to
allow the slave to begin or possibly complete a device-
internal phase including any internal actions that must
precede the subsequent bus access phase.
A61[8:42-51] (emphasis added). As explained above, this concept of allowing
DRAMs to respond to read/write requests in a specified time (i.e., a certain
number of clock cycles) requires an external clock that cycles periodically in the
background, regardless of whether any particular memory device on the bus is
transferring data. In this manner, the external clock can be used to govern[] the
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timing of a response to [a] transaction request, by allowing such responses to be
pre-scheduled. See, e.g., A60-61[6:64-7:10] (A request packet and the
corresponding bus access are separated by a selected number of bus cycles,
allowing the bus to be used in the intervening bus cycles by the same or other
masters for additional requests or brief bus accesses. (emphasis added)).
Consistent with the 097 specification, Rambus argued to the examiner that,
in the context of a synchronous memory device, an external clock signal
would be understood to be a periodic signal from a source external to the device
to provide timing information. A1068 (emphasis added). The examiner,
however, refused to adopt this construction, instead reasoning as follows:
The Examiner acknowledges that for example, figure 14
supports the use of a periodic clock signal; however, the
issue pertains to the scope of the claims and whether the
claims make any specific requirements. With respect to
claim 1, the first instance of an external clock signal
occurs when data is provided to the memory device. The
claim requires data to be provided with respect to a rising
edge transition of an external clock signal. In addition,
the claim also requires provid[ing] data with respect to a
falling edge transition of the external clock signal. The
claim does not disclose what actions are occurring with
respect to the clock signal before or after data is being
provided to the memory device.
A1068-69. Thus, the examiner concluded that the claims only require the clock
signal to be used during periods of data input (A1069-70), or in other words, the
claimed external clock can be intermittent and need only run when data is
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actually being written to memory. The examiner failed to explain, however, how
this could be consistent with the claimed synchronous memory device, which
undisputedly requires an external clock signal which governs the timing of the
response to [a] transaction request. A1067-68 (emphasis added).
The examiner determined that Inagaki discloses a synchronous memory
device with an external clock signal. Regarding the synchronous aspect, the
examiner simply relied on Inagakis shift registers (A1060), notwithstanding that
Inagakis shift registers operate for only a limited duration when signals 1 and 2
are being toggled (A2956; see also A1793[119]). Regarding the external clock
signal requirement, the examiner relied in part on the fact that Inagaki calls its
signal an external clock. A1061. The examiner acknowledged, however, that
Inagakis signals operate only during periods of data output and data input and
are therefore not continuous beyond that short timeframe. A1068.
On appeal, the Board affirmed the examiner. The Board found that the
claimed external clock signal need only be periodic during a limited . . .
duration. A9. As evidence of the alleged understanding of the word clock by
skilled artisans, the Board did not cite any intrinsic evidence or the opinion of
experts. Instead, it cited the English translation of Inagaki and its repeated use of
the term clock, notwithstanding that Inagaki also uses clock generically to
refer to nonperiodic signals such as CE and CAS. Id. The Board also cited a
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dictionary definition from 1994 (four years after the effective filing date of the
097 patent), which stated that a clock is a source of accurately timed pulses,
used for synchronization in a digital computer. A8-9 n.5; see A36. But the Board
overlooked the rest of that dictionary definition of clock, which included that it
usually contain[s] a means for producing a regularly recurring action. A36
(emphasis added).
The Board also never acknowledged the definition of synchronous memory
device adopted by the examiner, which specifically requires an external clock that
governs the timing of the response to [a] transaction request. A1067-68
(emphasis added). The Board never explained how Inagakis intermittent signal
which is only present during data transfercould possibly be used to govern the
timing of a response to a read or write request. In fact, this capability requires an
externalclock that cycles periodically in the background, regardless of whether a
particular device on the bus is actively transferring data.
3. Despite This Courts Construction Requiring aSeries of Bits, the Examiner and the Board
Nevertheless Found Write Request to Be Satisfied
by Inagakis Conventional, Transition-Based Signals
Neither the examiner nor the Board construed the term write request.
Nevertheless, the examiner found that Inagaki performs a write operation based
on its disclosure that its circuit is capable of reading . . . data into the memory
cells. A1060 (quoting A2955). He did not address the way the write operation
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command of Inagaki is allegedly transmitted or whether it employs a series of
bits, as this Courts construction of write request specifically requires. A1070-
71; see Infineon, 318 F.3d at 1093.
The Board affirmed the examiners rejection based on Inagaki, again
offering no construction of write request. A9-14. Instead, the Board simply
assumed that write request did not require a series of bits, contrary to this
Courts construction of that term. A12; see also A13 ([C]laim 1 does not define a
write request as a series of bits.). Indeed, at oral argument, the Board
questioned whether it should be bound by this Courts previous construction of
write request. A1003-04.4
To explain its departure from this Courts construction of write request,
the Board stated that Rambuss expert, Mr. Murphy, had conceded that a write
request did not have to be a series of bits. A12-13. Yet the Board relied only on a
partial sentence from Mr. Murphys declaration. Mr. Murphys full opinion was
that Inagakis transition-based signal . . . would not constitute a write request or
an operation code. Write requests and operation codes are made up of bits or the
4The Boards line of questioning was apparently based on the assumption that the
PTO is not bound by Federal Circuit constructions during reexamination because
the PTO uses a different claim-construction standard, i.e., the broadest reasonable
interpretation. See A1003-04. As the examiner had already conceded, however,
because the 097 patent is expired, the broadest reasonable construction no longer
applies. See A1043.
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state of a signal at a particular time, whereas asynchronous memory devices . . .
did not use bits to relay commands. Instead they relied on the transitions of signals
. . . rather than their state at a particular point in time. A1810[20]; see A12-13
(Board adding emphasis). Mr. Murphy thus used the word or to equate the state
of a signal at a particular time with bits, since, in a synchronous memory
device, a bit (0 or 1) corresponds to the state of a signal at a particular time (high or
low). A1810[20]. The Board, however, mistook Mr. Murphys use of the word
or as a concession that the state of a signal was an alternative to a series of
bits in a write request. A12-13.
The Board then supported its decision with the request packet, which is
described in the specification as carrying a series of bits but is not claimed. A13.
Although this Court had already considered the request packet in construing write
request to require a series of bits,Infineon, 318 F.3d at 1092-93 (finding that four-
bit AccessType field contains the read (or write) request and that request packet
includes other fields), the Board analyzed the request packet differently (A13).
The Board determined that, because the request packet is different from the write
request, and the request packet carries a series of bits, the write request then cannot
carry a series of bits (id.), flatly contrary to this Courts determination, cf. Infineon,
318 F.3d at 1092-93.
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Finally, the Board relied on dependent claim 2, which states that the write
request includes an operation code. A13 (citing A70[25:7-8]). According to the
Board, since the operation code may be one bit, the write request must therefore
also be allowed to be one bit (A13-14), notwithstanding that claim 2 says the write
request includes an operation code and therefore can also include other things
(A62[9:38-64]).
As a fallback, the Board reasoned that even if claim 1 somehow requires a
series of bits, the series can be a series of one bit. A13-14 & n.7. Yet the Board
provided no evidence that the word series is ordinarily understood to encompass
just oneobject or thing.
D. The iAPX Obviousness Rejection1. iAPX Does Not Disclose a Double Data Rate, and It
Uses Both Edges of Its Clock Signals for Other
Purposes
iAPX discloses a system designed by Intela Rambus licensee
(A2099[98])in 1982. A2969. There is no dispute that iAPX lacks the dual-
edge/double-data-rate feature recited in all of the claims-at-issue. A22; A1078-79;
see A1794-95[125-27]; A1811-13[22-28]. In fact, iAPX discloses using the
rising and falling edges of both of its clock signals for purposes other than double
data rate (only one edge of one clock signal is used for data transfer).
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Specifically, iAPX discloses two clock signals, CLKA and CLKB. A3285;
see A3230[7:12-19]. Several pieces of information are carried on both edges of
both clocks, including buffer directional control on CLKB. A3285 (showing
information on the output drive of both edges of both clocks); A3230[7:12-19].
The buffer directional control occurs between data transfers and is used to
configure the memory control unit to either receive data or output data.
A1795[127]; A1811-12[23-24]. Thus, if both rising and falling edges of CLKB
were modified to be used for data transfer instead of directional control, the
memory control unit would not be able to reconfigure from reading data to writing
data or vice versa. A1795[127]; A1811-12[23-24].
Moreover, for data transfers in the iAPX system, data must be held on the
memory bus for a full cycle of CLKB (a rising edge and a falling edge), thus
precluding a separate data transfer on the other of those edges. A3290 (showing
data being maintained over course of full clock cycle); A3331 (same). Thus,
because both edges of both clocks are necessary for the operation of the iAPX
device, they cannot be used to add a double data rate for data transfer. See A3285;
A3290; A3331.
Furthermore, iAPX operates at a low speed of 10 MHz (as compared to the
500 MHz speed of the 097 patent). Accordingly, a skilled artisan in 1990 wishing
to double iAPXs data rate would not be motivated to implement a dual-
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edge/double-data-rate feature to achieve that goal but, instead, would simply
increase the clock speed to 20 MHz. As Rambuss expert, Mr. Murphy, explained,
[i]f confronted with a system that could operate at 20 MHz, but was limited
because it only had a 10 MHz clock, one of ordinary skill in the art would have
understood to simply increase the clock frequency to 20 MHz and would not have
looked to modifying the system to use both edges of the clock signal.
A1812[26]. Mr. Murphy explained that, unlike adding data transfer on both
edges, there is no impediment to increasing the clock frequency. Id.
2. The Examiner Erroneously Believed iAPX Does NotUse Both Edges of Its Clock Signals for Other
Purposes
The examiners iAPX rejection was based on a fundamentally flawed
understanding of how the iAPX system works, as the Board tacitly acknowledged
on appeal. Specifically, in response to Rambuss argument that iAPX could not be
modified to transfer data on both edges of its clock signals because it already uses
both edges for other purposes, the examiner erroneously stated:
The Examiner notes that the Patent Owner[s] reason is
based on the erred assumption that both clock edges of
CLKB are being used for something specific. The
Examiner maintains that the, the iAPX 432 system doesnot show that all edges are used.
A1113.
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This statement is flatly incorrect. See, e.g., A3285. Indeed, the Board
tacitly conceded as much by repeatedly acknowledging that iAPX does, in fact, use
both edges of both clock signals for other purposes. See, e.g., A22 (The iAPX
system employs dual edges of two different periodic clocks . . .); A23 (. . . but
the iAPX system already employs dual clock edges as Rambus acknowledges.).
3. Despite iAPXs Use of Both Edges of Its Clock Signalsfor Other Purposes, and Despite the Examiners
Failure to Recognize This Fact in His Rejection, the
Board Nevertheless Concluded that It Would Have
Been Obvious to Modify iAPX to Perform the Double-Data-Rate Technique of Inagaki
On appeal, the Board affirmed the examiners obviousness rejection (which
was based on an erroneous understanding of iAPX), but for different reasons.
A22-33. The Board acknowledged that iAPX already uses both edges of its two
clocks, contrary to the examiners erroneous assumption. A22-24. The Board then
justified its finding that the edges could nevertheless be used for double-data-rate
data transfer by stating that iAPX already has the circuitry available to
send/receive data on both edges. A23. The Board hypothesized several different
ways iAPX could have been modified to incorporate the double-data-rate feature of
Inagaki, going far beyond any of the findings made by the examiner and often
failing to cite any supporting evidence in the record.
Hypothesis 1: iAPX Could Be Converted to a Write-Only Device. Even
though iAPX uses both edges of its CLKB clock for other purposes, including
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buffer directional control (i.e., switching between reading and writing), the Board
concluded that directional control was not required because claim 1 does not
require two-way traffic implicit in buffer directional control. A24. In other
words, the Board found that claim 1 does not require the ability to both input and
output data, even though the Board itself stated earlier in its opinion that, to
function as the well-known RAM[, a device must] perform input and output
(I/O) of data. A10. In short, the Board surmised on appeal that iAPX could be
modified to be a write only device (allegedly within the scope of claim 1), where
data can be written to memory but never retrieved.
According to the Board, those skilled in the art would have allegedly been
motivated to downgrade iAPX into a write-only device because [s]uch a
modification would create a cleaner memory device for handling mere one-way
data transfers embraced by broad claim 1. A25. Yet the Board never explained
why anyone would want a memory device that can only write data but never
retrieve it, nor why a person skilled in the art would have chosen to ignore the
express teachings of iAPX, which emphasize the need to both store and retrieve
data. See, e.g., A2986 (The MCU [Memory Control Unit] accepts variable length
data requests from the memory bus and performs the necessary access sequencing
to read or write the data. (emphasis added)). The Board cited no evidence that a
write-only device would have any practical utility or that anyone skilled in the art
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would have actually been motivated in 1990 to degrade the performance of iAPX
in order to create such a device.
Hypothesis 2: iAPX Control Signals Could Be Carried on Other Edges.
The Board alternatively surmised on appeal that a skilled artisan could have
provided buffer directional control with other CLKA or CLKB edges (A24
(emphasis added)), despite having acknowledged that these other edges are already
being used for other purposes (A22). As support for this hypothesis, the Board
cited only to a footnote in NVIDIAs brief, which simply repeated the same
conclusory statement without any evidentiary support. See A24 (citing NVIDIA
Resp. Br. 12 n.25 [sic, n.23], or A2772 n.23).
Hypothesis 3: The Slower Inagaki Clock Could Be Used as a Trigger for
CLKA and CLKB. The Board next surmised on appeal that it would also be
possible to combine Inagaki with iAPX without dropping any iAPX functions.
A25. This would allegedly be accomplished by modifying iAPX to include the
external slower Inagaki clock as a trigger for the faster CLKA and/or CLKB
thereby retaining all existing [i]APX functions. Id. The Board hypothesized how
this could be done: The slower external clocks rising and falling edges would
simply trigger the existing CLKA and CLKB, with the external clocks rising and
falling edges corresponding to the existing rising edges of faster CLKB and/or
CLKA, and the latter clocks retaining all functions. A26. Yet the Board cited no
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expert opinion or other record evidence to support this hypothesis, i.e., that a
person of ordinary skill in the art in 1990 would have been motivated to add a
redundant master clock to the two clocks of iAPX. A25-26. And, again, the
examiner never made any such finding in support of his obviousness rejection.
Hypothesis 4: Hold Data for Less Than Full Cycle. In response to Rambuss
argument that iAPX requires holding data over successive rising edges of CLKB
(thereby rendering the dual-edge/double-data-rate technique infeasible), the Board
theorized several different ways to modify iAPX to alleviate this defect. See A26-
28 (suggesting those skilled in the art could have modified [the iAPX data] to be
held for less than the time defined by the CLKA pulse, or [extended] . . . the
CLKA pulses (A28), or simply used a faster device[ ] than iAPX ( id.). Again,
the examiner never made any such findings, nor is it clear how any of the Boards
hypothetical devices would work.
In summary, the Board substituted its own hypothetical modifications to
iAPX for the examiners analysis, which was based on the erroneous assumption
that both edges of CLKB were not being used. Despite Mr. Murphys unrebutted
declaration and other Rambus evidence specifically explaining why such
modifications to iAPX to use a double data rate would not be feasible or obvious to
the skilled artisan (A1795[127]; A1811-12[22-25]; A1711), the Board stated
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that Rambus fail[ed] to present evidence that skilled artisans would have been
unable to modify interrelated parts to accomplish those new modifications (A25).
4. The Board Dismissed the Objective Evidence ofNonobviousness
Rambus showed that there was a long-felt need for faster memory and initial
skepticism of Rambuss solution. Specifically, by 1990, when the 898 application
was filed, many recognized the need for a solution to the drawbacks inherent in
transition-based memory devices. See A2617 (In 1992, the bottleneck problem
[was] one industry groups [had] tried unsuccessfully to solvefor years (emphasis
added)); A2623 (The problem Rambus addresses is well known to systems
designers.). But the industry was skeptical of the solution proposed by
Drs. Farmwald and Horowitz. See, e.g., A2100[105]; A1770[30]. Even as
Rambus explained its technology, potential licensees were concerned whether a
computers drivers and receivers could work at these frequencies. A2625
(March 1992); see also A2638 (system companies were skeptical that [Rambus
could] operate reliably at these speeds).
Rambus also showed that its invention has succeeded, based specifically on
its combination of a synchronous memory device with a double data rate. When it
was finally tested, Rambuss DRAM technology was widely considered
revolutionary in the industry. A2098[91]; see A2615 (March 1992, Rambus
had a revolutionary memory chip technology offer[ing] a tenfold speed boost to
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memory chips); A2632; A1770[29]; A2639; A2643; A2620 (calling Rambuss
approach a fundamental change in the design of computer memory systems).
Even in 1992, early in Rambuss existence, it was clear to reviewers that none of
Rambuss competitors come anywhere close to Rambus performance. A2642.
Articles touted the dual-edge/double-data-rate feature as a big factor in
increasing the speed of Rambuss synchronous devices. One article in 1992
described the revolutionary memory interface as provid[ing a] 500 Mbyte/s
memory interface and operating with a 250-MHz clock and transferring a byte of
data on each clock edgeone byte every 2 [nanoseconds]. A2633; see also
A2105[145]. Another 1992 article described how Rambus replaces all [the
existing] subsystems with a solution . . . capable of transferring data at 500 MBps
by using both edges of a 250-MHz clock. A2623; see A2639 (Transfers are
made on both clock edges, thereby doubling the bandwidth to 500 Mbytes/s.).
Indeed, Microna Rambus competitorhas specifically touted and still touts the
benefits of using both edges of a clock signal with synchronous DRAM as
revolutionary and pioneering. A1711. Specifically, it stated, [w]hen we
introduced DDR [double data rate] SDRAM, it was a revolutionary and pioneering
technologyenabling applications to transfer data on both the rising and falling
edges of a clock signaland vastly improving performance over SDRAM. Id.
(emphasis added).
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Moreover, Rambuss success is evident from its many licensees, including
Intel, which designed the system described in iAPX. By June 1992, Rambus had
signed technology license agreements with three of the top five DRAM
manufacturersNEC, Toshiba, and Fujitsu. A2624-25; A2099[98];
A2103[135]; A2627 (two of those manufacturers signed up right away). By
January 1994, Rambus had signed license agreements with four other
manufacturers, including Intel. A2099[98]. Since then, Rambus has added seven
more to the list, including NVIDIA, which requested this reexamination. A1761;
A3. Indeed, Rambus secured licenses from those major market players despite the
predictions of market forecasters that Rambus would have difficulty selling its
technology because [y]ou dont find Intel trying to accommodate some idea they
didnt think of. A2630.
The Board first dismissed the evidence of a long-felt need for higher
memory performance because the claims do not specifically claim higher
performance or recite a specific clock speed (A30), even though the claims
specifically recite the inherently faster synchronous memory device and
inherently faster double data rate. Regarding long-felt need, the Board asserted
there was no need for the invention because it allegedly already existed, as shown
by its separate rejection of the claims as anticipated by Inagaki. A30-31. But the
Boards obviousness rejection was an alternative to the anticipation rejection and
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presumed that the claims were not anticipated. The Board also dismissed
Rambuss evidence of a long-felt need in the art because some of the evidence was
from after the effective filing date of the 097 patent (A30), notwithstanding the
evidence of a long-felt need from before the effective filing date.
Regarding Rambuss evidence of commercial success, the Board simply
stated that Rambus has not established that any commercial success is
commensurate in scope with the broad reach of the claims. A31. Declining to
further elaborate, the Board alternatively stated summarily that the evidence of
commercial success did not rebut the obviousness of the claimed features based
on the applied prior art. Id.
Turning to Rambuss success in licensing the Farmwald patents, the Board
faulted Rambus for not selling any products and relying solely on licenses (A31),
despite Rambuss uncontroverted evidence that the very nature of its business
required it to operate as a licensing company rather than building DRAMs (A2093-
94[58-60,64]; A2625 (Rambus was more or less forced into its technology
licensing role by the size of the undertaking)). The Board also faulted Rambus
for not explaining the scope of its licenses (A31-32), even though the licenses
specifically covered the appealed claims of the 097 patent (see, e.g., A3 (stating
that NVIDIA settled the dispute over the 097 patent with Rambus); A1770[29]
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(numerous companies . . . have licensed the inventions claimed in [the 097]
patent)).
Finally, regarding the praise for Dr. Horowitz and his invention (A2602-03
(received IEEE award for increasing memory access bandwidths); A2607 (elected
to National Academy of Engineering)), the Board faulted Rambuss evidence for a
lack of nexus with the claimed invention or for the contribution of other unclaimed
features (A32-33), notwithstanding Rambuss specific evidence of praise for the
addition of a dual-edge/double-data-rate feature to a synchronous DRAM as a
revolutionary and pioneering technologyenabling applications to transfer data on
both the rising and falling edges of a clock signaland vastly improving
performance over synchronous DRAM alone (A1711).
IV. SUMMARY OF ARGUMENTIn finding some of the appealed claims anticipated by Inagaki and all of
them obvious based on iAPX in view of Inagaki, the Board reversibly erred in its
claim-construction and validity analyses.
By allowing external clock signal to encompass signals that are
intermittent and not continuously periodic (and thus incapable of supporting the
claimed synchronous feature), the Board implicitly construed this term contrary
to the relevant intrinsic and extrinsic evidence. And by declining to require that a
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write request contain a series of bits, the Board ignored the earlier construction
given by this Court, which specifically requires a series of bits.
In holding the 097 patent obvious by adding a dual-edge/double-data-rate
feature to iAPX, the Board rationalized its rejections through hindsight and
conjecture, ignoring the evidence that this combination would have been infeasible
and beyond the purview of those of ordinary skill in the art in 1990. Rather than
relying on Rambuss unrefuted evidence or the examiners reasons for his
rejection, the Board hypothesized ways in which iAPX would have worked if it
had been designed differently. The Board also erroneously dismissed Rambuss
objective evidence of nonobviousness, which strongly rebuts the Boardspost facto
theory of obviousness.
V. ARGUMENTA. Standard of Review[C]laim construction by the PTO is a question of law that [this Court]
review[s] de novo. In re Baker Hughes Inc., 215 F.3d 1297, 1301 (Fed. Cir.
2000). Anticipation is a question of fact reviewed for substantial evidence. In re
Suitco Surface, Inc., 603 F.3d 1255, 1259 (Fed. Cir. 2010). Obviousness is a
question of law that [this Court] review[s] de novo with underlying factual
findings. In re NTP, Inc., 654 F.3d 1279, 1297 (Fed. Cir. 2011); see also In re
ICON Health & Fitness, Inc., 496 F.3d 1374, 1378 (Fed. Cir. 2007) (Although
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based on determinations of underlying facts, which we review for substantial
evidence, the ultimate conclusion of obviousness is a legal question, which we
review de novo.).
B. The Board Erred in Implicitly Construing External ClockSignal to Include Intermittent, Nonperiodic Signals
Regarding the claimed external clock signal, although not offering any
explicit construction, the examiner and the Board made clear that they did not
require the external clock signal to be continuously periodic, such that it is
capable of governing the timing of a response to a transaction request. Supra
III.C.2. That was error, as the language of the claim itself, the specification, the
prosecution history, and even the dictionary definition that the Board relied on all
make clear that the external clock signal must be continuously periodic on the
bus, irrespective of whether any particular DRAM device is in use.
The language of the claims makes clear that the external clock signal must
be continuously periodic because the claims recite a synchronous memory
device, which, as the examiner agreed, means a memory device that receives an
external clock signal which governs the timing of the response to [a] transaction
request. A1067-68 (emphasis added). As explained in Section III.A.2, supra, in
order to govern the timing of a response, the clock signal must be continuously
periodic, not only while a particular memory device is active but also while it is
inactive (e.g., when it is waiting to deliver requested data). That is, the clock
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signal must be predictable such that the memory controller can request that data be
returned in, e.g., two clock cycles, and those cycles must then occur even though
the targeted DRAM is not actively transferring data during that time. Thus, the
claim language itselfi.e., the recitation of a synchronous memory device
makes clear that the claimed external clock signal is continuously periodic, such
that it can govern the timing of a response to a read/write request.
The specification likewise makes clear that the claimed external clock
signal must be continuously periodic because this is the only type of clock signal
that is disclosed and described. Supra III.B.3. Indeed, the specification
repeatedly refers to waiting a specified number of clock cycles before returning
data. For example, the specification explains that a request packet and the
corresponding bus access are separated by a selected number of bus cycles,
allowing the bus to be used in the intervening bus cycles. A61[7:7-10]. Allowing
the bus to be used during the interval between a request and the data being returned
allows for increased speed and efficiency, which are major goals of the 097
patent. A60-61[6:64-7:16]. In order for those intervening bus cycles to exist, the
external clock must keep cycling and, therefore, must be continuously periodic
throughout the operation of the entire system, regardless of whether a particular
memory device is actively transferring data.
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The prosecution history also demands this construction. During prosecution
of the related 281 Farmwald patent, the examiner applied a prior art r
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